[time-nuts] Noise of digital frequency circuits (was: Programmable clock for BFO use....noise)

Magnus Danielson magnus at rubidium.dyndns.org
Fri Nov 9 17:34:21 EST 2018



On 9/16/18 11:06 PM, Attila Kinali wrote:
> Moin,
> 
> On Sat, 15 Sep 2018 08:38:55 -0700
> "Richard (Rick) Karlquist" <richard at karlquist.com> wrote:
> 
>> On 9/15/2018 3:26 AM, Attila Kinali wrote:
>>
>>> possible logic family for the task. Otherwise the harmonics of the
>>> switching of the FF will down-mix high frequency white noise down
>>> to the signal band (this is the reason for the 10*log(N) noise scaling
>>> of digital divider that Egan[1] and Calosso/Rubiola[2] and a few others
>>> mentioned).
>>
>> Wow, I never knew this in 45 years of designing synthesizers!
>> I do remember that some of the frequency counter engineers at HP
>> talked about noise aliasing.  I think this is another way of
>> describing the same problem.
> 
> Yes. This effect has been known for a few decades at least.
> What kind of puzzles me is, that I have not seen a mathematically
> sound explanation of it, so far. People talk of aliasing and sampling,
> but do not describe where the sampling happens in the first place.
> After all, it's a time-continuous system and as such, there is no
> sampling. One could look at it as a (sub-harmonic) mixing system,
> but even that analogy falls short, as there is no second input.0
> It also fails at describing why there is not infinite energy being
> down-mixed, as the resulting harmonic sum does not converge.

A single diode mixes, hence no secondary port. The double-balanced mixer
is what you get when using transformers and four diodes to cancel out
the input signals, but a single diode suffice if you can handle the
original signal and the mix products.

There will be no infinite energy, for very trivial reasons. While you
might think that integration (or actually summation) of a 1/n series
would not converge, the actual life situation is not a 1/n series, since
the rise/fall time creates a -6 dB/Oct slope in itself, resulting in a
-12 dB/Oct slope for higher N, and hence the full series converge. This
also means that the mixed down noise has finite result. It is thus the
trivial bandwidth limitation of the system kicking in. Obvious from
basic EMC training.

> If someone knows of a description that goes beyond handwavy arguments,
> I would very much appreciate hearing of them.
> 
> The only way to explain the effect in a rigorous way, that I could
> figure out, is to apply Hajimiri and Lee's Impulse Sensitivity Function[1],
> and adapt from the oscillators they discribed to general periodic systems.
> (The step, as one can guess, is small, but hic sunt dracones)
> Doing this, it becomes obvious that the down-mixing is an inherent
> property of all systems that use or generate non-sinusoidal waveforms.
> It is this ISF that is the source of the down-mixing/aliasing effect,
> as it has a periodic waveform of sharp spikes.

Downmixing is a result of non-linearity. Feed a perfect sine in there,
and it will downmix on overtones for you. That is how non-linearities
such as diodes work. Look on the Taylor expansion of the exponential
function or logaritmic function and think what pure sine + noise will do
there. It is usually easier to analyze by modeling the noise as a small
sine. Each x^n in the Taylor expansion will create a rich set of
products, consider the noise sine to be near a perfect multiple of the
base sine and out pops these products.

> As the ISF is probably (this is my intuition and I have, unfortunately,
> no proof of this) related to the derivative of the produced output waveform,
> it becomes important to limit the slew rate of the output, to introduce
> a second pole in the ISF and thus limit the number of harmonics.
> Yet, it is also important to keep the input slew rate high, in order to
> keep the width/height of the ISF pulses low.
> 
> A partial discussion of this can be found in the paper I presented
> at IFCS earlier this year[2]. Unfortunately, the write-up is not
> nice and I only realized after the deadline that I should have
> all written it using a different approach. Sorry for that.
> If something is not clear, do not hesitate to send me an email.
>  
>> About 10 years ago, the frequency synthesizer chip vendors started
>> talking about a Figure of Merit (FOM) that predicted phase noise floor, 
>> and it also included the 10 LOG N noise scaling.  An application 
>> engineer at ADI told me this was a characteristic of the sampling phase 
>> detector that all these chips used.  But I always wondered if the 
>> frequency divider could come into play.  The way FOM is defined,
>> it doesn't distinguish between phase detector and divider noise.
> 
> The 10*log(N) also applies to the phase detector in PLL chips,
> where N becomes the ratio of the phase detector bandwidth divided
> by the phase detector input frequency.
> 
> Given that the phase noise is dominated by the input source' phase
> noise, there will be no appreciatable difference in whether the
> down-mixing happens in the divider or the phase detector, as long
> as the bandwidth of all components is the same. If the bandwidth
> is different, we get into something akin Collins' zero crossing
> detector[3] where appropriately designed stages with different
> input bandwidths limit the energy that is down-mixed.
> 
>> At Agilent, we used to make a lot of lab demos using a Centellax
>> (now Microsemi AKA Microchip) frequency divider that could divide by any 
>> number between 8 and 511 up to 10 GHz.  It was absolutely fabulous for 
>> dividing 10 GHz down to 2.5 GHz.  But 20 LOG N quit working if I tried 
>> to divide down to 50 MHz.  Now you have explained it.
> 
> Hmm? Are you implying those chips somehow were able to give
> a 20*log(N) phase noise behaviour? If so, do you know how
> they achieved such a feat?

The phase noise scales with frequency this way. The time-noise is the
same, it's just that you now have N cycles between the occurrence of
time, so N times lower in amplitude or 20 log(N) in dB. However, that is
for a theoretically perfect divider, so eventually you hit the noise
floor of the divider. Perfectly well described in the NIST library.

>>> If you divide by something that is not a power of 2, then it is important
>>> that each stage produces an output waveform with a 50% duty cycle. Otherwise
>>> flicker noise which has been up-mixed by a previous stage, will be down-mixed
>>> into the signal band, increasing the close-in phase-noise.
>>
>> Wow, another thing I never knew.  
> 
> I do not think that anyone was aware of this. A least I do not remember
> seeing this being mentioned in any of the papers I have read.

Read the old NIST stuff, it's in there. This is also why they prefer to
do odd division and "clean up" with a separate divide by 2.

> I, myself,
> stumbled over it by accident. I was trying to design a sine-to-square
> wave converter and wanted to understand what happend to the noise.
> Especially the AM to PM conversion that a few people here have mentioned
> a few times. I was looking at Claudio's measurement [4, page 28] and,
> after applying Hajimir and Lee's ISF, I could (mathematically) explain
> everything but what Enrico so nicely labled as "bump". None of the
> explanations that I exchanged with Enrico, Claudio, Magnus and a few
> other people made sense with the complete data. An external influence
> didn't make sense as the flicker noise went from a straight ~6dB/oct line
> to a straight ~3db/oct line below 25MHz. This hunch got stronger when
> Claudio shared the complete circuit they used with me(see figure 3 in [2]).
> The feedback circuit, which stabilizes duty cycle, has a -3dB frequency
> of 0.28Hz, which is exactly the frequency where the bump is. And below
> it, the flicker noise behavior seems to go back to approximately 6dB/oct.
> For a complete explanation, see my paper[2] section 5.D "Scaling in a 
> Multi-Stage Sine-to-Square Converter."

Not the first or the last time a control loop ads a hump. If made
simple, you get amplification gain. PLLs do it on their resonances for
instance, which is why they need to be well damped.

>> The conventional wisdom was to
>> divide by any number (even or odd) and then follow that divider
>> with a divide by 2 flip flop to get 50%.  Now, that is in question.
>> The now correct answer is to us a variable modulus prescaler to
>> divide by P and P+1, controlled by a toggle flip flop to make
>> half the divisions at P and half at P+1.
> 
> I don't think the modulus prescaler is a good approach.
> It will help reduce flicker noise, at the price of incrased
> white noise, as the two division values will generate two
> frequency spikes in the ISF that are close to each other.
> There is probably some residual even harmonic content due to
> the switching betwen the two scaler values, which will increase
> flicker noise, not as much as having non-50% duty cycle, but still.

It will just add systematic phase-noise. The divide by 2 rather
down-mixes with out of phase variants so it to some degree self-balance.
Also, 50% has zeros on even frequencies but as you shift away from 50%
you start to add power on even overtones. That's what PWM does for you.

> The right way to do it is to use both edges in case of odd division
> factors (as some of the divider circuits by Linear/Analog seem to do).
> Alternatively generate a ramp/sine output, ie use a Λ-divider
> or a DDS, as both have much lower harmonics content in the ISF
> and thus do not suffer from the down-mixing as much. If a square
> waveform is required afterwards, a square-to-sine converter with
> approriate bandwidth for the output frequency will solve that.

Sine with just sufficient bandwidth, then into square-to-sine converter.
No high-Q filters around.

Cheers,
Magnus



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