[time-nuts] PLL/GPSDO/etc learning resources for mere mortals

Forrest Christian (List Account) lists at packetflux.com
Mon Sep 3 07:33:15 EDT 2018

Thanks to everyone who has responded so far.

My underlying interest is learning about 1PPS holdover methodologies in the
presence of environmental changes (think outdoor day/night temperature
cycles).  My thoughts are that there are two ways that seem obvious to me
to implement a temperature-stable holdover:

1) Discipline an OCXO using some sort of control loop to a known frequency
(using an appropriate GPS receiver) and divide that down to 1 Hz.   This
solution has large parts in the analog domain, with a bit of a PID or other
similar control loop implemented in a micro, and the divider perhaps in a
FPGA or implemented with standard logic.  The challenge seems to me to be
how to temperature stabilize the entire DAC chain without putting it all in
an oven - on the other hand, it seems that this might not be quite as
critical as I think it is, due to the relatively limited frequency control
range of many OCXO's in comparison to the voltage range of that signal. But
I just don't know enough to be able to say for sure.  I probably need to
get a few surplus (or new) OCXO's and play with them.

2) Use a non-disciplined OCXO as a temperature-stable clock and feed this
clock into a FPGA where one could implement a 1Hz PLL or similar.   It
would seem to me that even measuring the OCXO's average frequency over a
long period using a GPS 1PPS source as a gate would get me somewhere toward
where I am headed, but I'm guessing that there's a lot of complexity I'm
not aware of.

I realize that a lot of what I just mentioned above contains a lot of
naivete.  I'm sort of at the stage that I sort of know what building blocks
I might be able to use (and perhaps these aren't even the right blocks),
but need to understand more about the internal workings of each.   There's
also the distinct possibility that I'm missing key building blocks that I
don't even know exist (or that they're needed).

I'm going to dig through "Deans Book" and see about obtaining a non-scarily
priced copy of the Phase Lock Techniques by Gardner.   Both seem like
excellent resources that will take me some time to digest.  Any other
suggestions would be happily received.

On Mon, Sep 3, 2018 at 12:49 AM, Hal Murray <hmurray at megapathdsl.net> wrote:

> lists at packetflux.com said:
> > I'm trying to fill in some gaps in my knowledge about PLL's, GPSDO's,
> etc.,
> > with the goal to eventually implement some of these either in a
> > microcontroller or fpga or some combination thereof.
> An FPGA is unlikely to be the way to go for a GPSDO.  There is lots of
> time to
> do it in software and the tools for micros are generally easier to work
> with
> than FPGA tools.  (But if you like FPGAs, don't let me scare you away.)
> One thing to keep in mind for GPSDOs is that the time constants for
> filters
> are very long relative to what is reasonable to build with Rs and Cs that
> are
> readily available.  The usual way to go is a D/A connected to a micro.
> That
> moves the filter time constant into software.  Thus you will see lots of
> discussion on this list about which D/A to use.  Generally, you would like
> more bits than you can get.  For a one-off project, you can trade a
> reduced
> tuning range for better resolution if you are willing to use a pot (or
> soldering iron) for the coarse adjustment, aka the high bits on the tuning
> range.
> Another thing to add to your list is hanging bridges and sawtooth
> correction.
> Another magic term associated with PLLs is PID controller - Proportional,
> Integral, Differential.  You may find some web articles that tell you
> enough
> to be helpful without using complicated math.
> --
> These are my opinions.  I hate spam.
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*Forrest Christian* *CEO**, PacketFlux Technologies, Inc.*
Tel: 406-449-3345 | Address: 3577 Countryside Road, Helena, MT 59602
forrestc at imach.com | http://www.packetflux.com
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