[time-nuts] Lars GPSDO on EEVblog

[Bruce Griffiths]

Use the phase detector output to drive the tristate control input of a fast CMOS tristate state buffer (eg 74HC126 or faster) which in turn drives the RC network eliminating the diode.
Then correct for the exponential charging characteristics using the micro.

For best results increase ADC resolution by 1 bit or more and set RC charge time constant to around the maximum expected time interval.
Using a 2 stage synchroniser to drive the tristate control input of the buffer to minimise metastability issues may also be useful.

Even linear Time to amplitude converter circuits using a current source exhibit nonlinearities. Its easy enough to calibrate the nonlinearity of a simple TAC.

Bruce
 
> On 09 September 2018 at 14:17 Jim Harman <j99harman at gmail.com> wrote:
> 
> 
> Charles wrote,
> >
> > According to my tests, the B-C junction of a high-quality 2N3904 has
> > about 50pA of leakage at 20vDC reverse voltage.
> 
> 
> That's good to know, but the problem I had with this circuit was with the
> forward current at a low forward voltage. With this phase detector, the
> HC4046 makes a 0 to 1 usec pulse representing the time difference between
> the 1 pps from the GPS and the 1 MHz derived from the OCXO. This charges
> the capacitor to a voltage proportional to the width of the pulse, the ADC
> measures the capacitor voltage, and the cap discharges through the 1 Meg
> resistor during the rest of the second.
> 
> When the HC4046 output goes low at the end of the pulse, the voltage on the
> other side of the 1N5711 diode goes down to about 0.4 V. With a 1N4148 or
> similar diode instead of the transistor, the forward current after the
> capacitor is mostly discharged through the 1 meg resistor is enough to
> prevent the capacitor from discharging all the way and the minimum voltage
> at the ADC is about 0.3 V. or about 120 counts on the ADC. I was able to
> get this below 90 counts by using the transistor. It might be possible to
> reduce the 1 Meg resistor, but then we risk significantly discharging the
> capacitor in the short time between the end of the pulse and the A/D
> reading.
> 
> I would certainly be interested in any suggestions on improving this
> circuit.
> 
> >
> >
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