[time-nuts] Programmable clock for BFO use....noise
attila at kinali.ch
Sat Sep 15 06:26:33 EDT 2018
On Fri, 14 Sep 2018 21:42:05 +0000
Bryan _ <bpl521 at outlook.com> wrote:
> I would be interested in hearing more of the more suitable classes of
> logic chips. I have a 20Mhz rubidium that I wanted to divide down to 10Mhz
Any logic family works, as long as it is fast enough to handle your
input frequency. Due to the non-linear (aka digital) behaviour
of a D-Flipflop style divider, it is recommended to use the slowest
possible logic family for the task. Otherwise the harmonics of the
switching of the FF will down-mix high frequency white noise down
to the signal band (this is the reason for the 10*log(N) noise scaling
of digital divider that Egan and Calosso/Rubiola and a few others
As a rule of thumb, I'd say that the FF should not be more than 10 to 20
times faster than the input frequency, to limit noise down-mixing.
If your FF is too fast or you want to reduce the noise floor, capacitively
loading and/or having some additional resistance in the Vcc and GND lines
will help slow it down. But ensure that the resistance is still low enough
that the FF's supply stays within specs at all time. Similarly, the
capacitive loading should be low enough that the output current is within
Alternatively, using the Λ-divider approach and introducing voltage
steps between 0 and 1 will also reduce down-mixing.
If you divide by something that is not a power of 2, then it is important
that each stage produces an output waveform with a 50% duty cycle. Otherwise
flicker noise which has been up-mixed by a previous stage, will be down-mixed
into the signal band, increasing the close-in phase-noise.
 "Modeling Phase Noise in Frequency Dividers," by Egan, 1990
 "The Sampling Theorem in Pi and Lambda Digital Frequency Dividers,"
by Calosso and Rubiola 2013
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