[time-nuts] Programmable clock for BFO use....noise

Gerhard Hoffmann dk4xp at arcor.de
Sun Sep 16 16:08:19 EDT 2018


Am 15.09.2018 um 17:38 schrieb Richard (Rick) Karlquist:
>
>> If you divide by something that is not a power of 2, then it is 
>> important
>> that each stage produces an output waveform with a 50% duty cycle. 
>> Otherwise
>> flicker noise which has been up-mixed by a previous stage, will be 
>> down-mixed
>> into the signal band, increasing the close-in phase-noise.
>
> Wow, another thing I never knew.  The conventional wisdom was to
> divide by any number (even or odd) and then follow that divider
> with a divide by 2 flip flop to get 50%.  Now, that is in question.
> The now correct answer is to us a variable modulus prescaler to
> divide by P and P+1, controlled by a toggle flip flop to make
> half the divisions at P and half at P+1.

Resynchronize the output of the divider to the undivided clock with 
another D-FF
and everything but that last D-FF will fall out of the equation for 
phase noise.

I'm also not a fan of using slowish, slew-rate challenged  logic as a 
replacement
for a low pass. When I want a low pass, I make it from nice, 
time-invariant RLC.

regards, Gerhard.





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