[time-nuts] Noise of digital frequency circuits (was: Programmable clock for BFO use....noise)

Mattia Rizzi mattia.rizzi at gmail.com
Thu Sep 20 06:31:01 EDT 2018


Hi Attila, everyone,
very interesting discussion!

>People talk of aliasing and sampling,
but do not describe where the sampling happens in the first place.
After all, it's a time-continuous system and as such, there is no
sampling.

I would say that the sampling occurs when you're using only a slice of an
input signal.  For instance, If you're using only the zero-crossing slice
of a sinewave to produce a divided version rather than the full envelope.
It's a matter of how you process information in your circuit.

>"A Physical Sine-to-Square Converter Noise Model,"
> by Kinali, 2018

I read the paper, very interesting as well!
I have a  minor remark, in the paper you relate the ISF (let's say
"sampling window") to the output slew rate of the comparator. I would say
that the sampling window should be related to the comparator input stage
bandwidth. If you have an high bandwidth input stage (e.g. 5 GHz) followed
by a slew rate limited output stage (e.g. 100 MHz) , high frequency noise
will trigger the output circuit and aliasing it. Viceversa, if you have a
low bandwidth input stage, even if the output stage is very fast, you don't
get input noise aliasing.

cheers
Mattia




Il giorno lun 17 set 2018 alle ore 13:46 Attila Kinali <attila at kinali.ch>
ha scritto:

> On Sun, 16 Sep 2018 23:06:06 +0200
> Attila Kinali <attila at kinali.ch> wrote:
>
> > [2] "A Physical Sine-to-Square Converter Noise Model,"
> > by Kinali, 2018
>
> Oops.. I forgot to add the link to the pdf, sorry
> http://people.mpi-inf.mpg.de/~adogan/pubs/IFCS2018_comparator_noise.pdf
>
>
>                                 Attila Kinali
> --
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