[time-nuts] PLL suggestions

[Dana Whitlow]

Don't forget the "regenerative" frequency divider concept, either.  At some
point you'll
need to do some division, and these things seem to have a rep for better
phase noise
performance than logic-based dividers.

Dana


On Tue, Dec 31, 2019 at 10:15 AM Dan Kemppainen <dan at irtelemetrics.com>
wrote:

> Hi All,
>
> We've got a project going on where we need a 125MHz clock that should be
> locked to 10MHz. I'm considering an on board 10MHz oscillator and
> external 10MHz input to utilize an external standard to lock the 125MHz
> which would PLL a 125MHz source.
>
> The 125MHz becomes a reference for 3.125Ghz, as well as logic running at
> 125Mhz. (Currently this system is running on small 125MHz TCXO.)
> Basically we need a reasonably clean 125MHz signal, but locked to 10Mhz
> for frequency reference.
>
> We've identified a few VCXO's that seem to be low noise and are small
> enough. The 10Mhz is easy enough. However my stumbling block is a simple
> PLL.
>
> What I'm looking for is a simple, small PLL chip. Something with
> external analog loop filter components to allow easy tweaking would be
> preferred.
>
> In my perfect world, this chip would be a COTS part, with pin strappable
> divider configuration or similarly simple hardware configuration. An OTP
> device would work as well, as would one with it's own memory and
> external programmer. If necessary a small PIC or similar could be used
> to configure the PLL, but that's one chip which would be nice to avoid.
>
> Smaller compact package SMT parts are fine. This is going on a board
> with lots of SMT components, leadless flat pack devices and BGA's, so
> smaller is better.
>
> If any of you have any suggestions, I'd appreciate it.
>
> Happy new year!
> Dan
>
>
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