[time-nuts] inexpensive fiber optic distribution

[Anders Wallin]

Unfortunately my notes aren't so great from 2017 when I tested some
versions of our SMA-to-SFP board, using BX10 (BiDir) optics and short 2m
fibers. (the lesson here is that one should immediately document and
publish/blog about things measured in the lab...)
The attached pictures will give you some idea of what to expect. The
measurements are residual phase-noise for a 10 MHz carrier. In other words
the DUT-arm contains: SMA-to-SFP -> SFP -> 2m-fibre -> SFP -> SFP-to-SMA.
With a another board or other SFPs (SFP+ for 10Gbit?) the results might be
different?
For reference a noise floor (passive-splitter to both DUT/REF) and
distribution-amplifier (see FDA/PDA project on ohwr.org) residual phase
noise are shown.

On some version of the board I tried a sine-to-square converter LTC6957
with not so great results (Mattia had similar experiences?).
Similar op-amps that work in distribution amplifiers seem to work OK if one
wants to buffer on the SFP-breakoutboard or buffer before/after a
transformer that converts single-ended to differential.

No reading/writing of the internal SFP memory is needed for these kinds of
tests.

Anders
[image: phase.png]
[image: phase_noise.png]
[image: tdev.png]
[image: adev.png]
[image: mdev.png]


On Fri, Mar 22, 2019 at 4:03 PM Mark Spencer <mark at alignedsolutions.com>
wrote:

> I'd be curious in these numbers as well.   When I used to deal with this
> type of an issue for a living I typically didn't worry much about
> consistent delays of well under a millisecond.
>
> I'd be curious to know what the typical numbers are.
>
> Mark Spencer
>
>
> mark at alignedsolutions.com
> 604 762 4099
>
> > On Mar 22, 2019, at 10:22 AM, Hal Murray <hmurray at megapathdsl.net>
> wrote:
> >
> >
> > bownes at gmail.com said:
> >> The infrastructure is easily enough interfaced to, even a simple
> >> microprocessor can do it, using switches allows for distribution with
> known
> >> characteristics.
> >
> > It would be interesting to  measure the delays through a switch.
> >
> > The switches are retiming the data stream.  It has to buffer up enough
> data
> > before it starts sending to make sure that it won't run out before the
> end of
> > packet if the switch clock is fast and the source clock is slow.  There
> is
> > also bit/byte synchronization, and crossing a clock boundary before
> things get
> > started.
> >
> >
> >
> > --
> > These are my opinions.  I hate spam.
> >
> >
> >
> >
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