[time-nuts] GPS 1PPS, phase lock vs frequency lock, design

[life speed]

Hi all, it's been a while since I visited.  I am venturing into an unfamiliar area from my usual low phase noise PLL, OCXO and microwave synthesizer design endeavors.
I recall there are some knowledgeable, well, time nuts on this list and hope you'll indulge some questions and maybe direct me to some appropriate white papers and share insights.
I want to discipline a 10 MHz OCXO with 1PPS from GPS.  Obviously not an unusual application, but I need to understand the methodology as I will not be buying a module but rather implementing the design with an FPGA, off-the-shelf GPS chip and a high-quality 10MHz DOCXO.
One of the first questions I have:  is it possible to implement phase-lock with a narrow digital PLL and DSP integrator/filter in the FPGA?  I suspect some 1PPS disiplined OCXO implementations are merely controlled to the same frequency, but not necessarily the same phase, depending on the details of the implementation.
I need the output of two of these units I design to have to be phase coherent relative to each other.  Your knowledge, experience and scholarly references are welcome.
Thanks,
Lifespeed