[time-nuts] GPS 1PPS, phase lock vs frequency lock, design

[Attila Kinali]

On Sat, 25 May 2019 00:51:46 +0000 (UTC)
life speed via time-nuts <time-nuts at lists.febo.com> wrote:

> I want to discipline a 10 MHz OCXO with 1PPS from GPS.  Obviously not an 
> unusual application, but I need to understand the methodology as I will not 
> be buying a module but rather implementing the design with an FPGA, off-the-
> shelf GPS chip and a high-quality 10MHz DOCXO.
>
> One of the first questions I have:  is it possible to implement phase-lock 
> with a narrow digital PLL and DSP integrator/filter in the FPGA?  I suspect 
> some 1PPS disiplined OCXO implementations are merely controlled to the same 
> frequency, but not necessarily the same phase, depending on the details of 
> the implementation.

As you state that you are familiar with PLL design, I guess your confusion
comes from having a 1Hz signal and trying to use that for a "normal" phase
detector. While this is possible and can be done, it leads imediatly to
the problems you have stumbled upon. The canonical way to do it, is instead
measuring the arrival time of the PPS relative to a clock derived from the
10MHz. Ie you timestamp the PPS. Then you take the timestamp modulo 1 second
and substract from it the setpoint value (can be 0 or anything else that
makes your math easier), which then gives you the error or your control
loop. Having the error value, you now can apply the digital PLL knowledge
you have and design the loop filter.

There are of course a few complications of the system:

1) You need to apply the saw-tooh correction to the measured PPS timestamp.
Otherwise you get a spread in the order of 10ns and, much worse, "hanging
bridges"

2) The systems sampling clock is 1Hz, which is unusual to most people
who are used kHz or even MHz sampling rate digital loops. But the advantage
is that it's so slow, that you can do all the calculations with minimal
dead time, compared to the sampling period. Just keep in mind that
everything has to have a sub-Hz bandwidth.

3) To achieve a decent frequency stability and low noise OCXO output,
the DAC you use to control it needs to have at the very least 16bit
(mostly DNL, but INL shouldn't change too much or too quickly, otherwise
the loop becomes unstable). For one of my design, I calculated that
I would need ~23bit for the stability I wanted, which poses a problem
by itself. Luckily, having the DAC in the control loop simplifies things
quite a bit. Using a 16bit DAC (eg AD5560 or AD5683R, the latter would
be better suited for this application due to the LDAC pin) and using
a delta-sigma modulator (at least 2nd order, better 4-8th order) 
should give you enough resolution to work with.

Alternatively, a 1bit DAC using a high order delta-sigma modulator
and an external D-FF (don't use one in the FPGA as the jitter from
the FPGA would kill the resolution) would also work. Audio DACs
don't work for this application as they have too much low-frequency
noise (aka drift).

4) The filter after the DAC will require some good opamps. Even though
using chopper/autozero opamps is tempting, I'd rather go for low flicker
noise bipolar opamps (eg LT6018 or LTC6081, LT6010,...) as the loop will
compensate for the drift of the opamp (given it's not too big). 

5) The easiest way to timestamp PPS if you already have a FPGA is
using a ring oscillator based TDC. There is code out there that
works for Xilinx[1]. I have a port to Altera/Intel Cyclone4 lying
around if you are interested. This will give you a resolution in the
order of 100-200ps, which should be good enough for a GPSDO.
The second way would be to implement a time-to-amplitude converter
(the simplest, I am aware of, is the one in Nick Sayer's GPSDO[2]),
but that is already quite a bit more effort in the analog domain
than what a ring oscillator TDC would require.

> I need the output of two of these units I design to have to be phase
> coherent relative to each other.  Your knowledge, experience and scholarly
> references are welcome.

There is not much out there on refernces that I could send you. Most
of what I know I gathered from looking at other peoples GPSDOs and
reading what they have done. An outdated summary of that can be found
at [3]. Additional to this you will need good knowledge of digital PLL
design, for which I recommend having a look at the standard books
(e.g. Gardner[4] and Best[5]).

How well you can get the GPSDOs synchronized depends a bit on the effort
you spend on the receiver. Standard L1 receivers (of the same model
with the same firmware) will be better than 10ns if they are not too
far apart (a few 10km to maybe 100km). If you need better than 1ns, you
will need an L1/L2 receiver and have to manually calibrate the offset
of the receiver.

HTH

			Attila Kinali


[1] https://ohwr.org/project/tdc-core/wikis/home
[2] https://hackaday.io/project/6872-gps-disciplined-xcxo
[3] https://attila.kinali.ch/blog/2016/02/07/gps-disciplined-oscillator
[4] "Phaselock Techniques", 3rd edition, 2015 by Floyd Gardner
[5] "Phase-locked lopps", 6th edition, 2009, by Roland Best
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