[time-nuts] A simple sampling DMTD

[Bruce Griffiths]

Merely selecting every 100th sample throws away the opportunity to reduce the effective ADC noise by digital filtering before decimation.

Bruce
> On 05 November 2019 at 10:08 Jan-Derk Bakker <jdbakker at gmail.com> wrote:
> 
> 
> Dear Scott,
> 
> You are entirely correct, sampling at 100ksps is mathematically the same as
> sampling at 10Msps and then decimating by a factor of 100. The reason I'm
> doing it in this way is driven by two practical considerations:
> 
> - my ADC, the LTC2140 (selected for bandwidth, dynamic range, aperture
> jitter and availability) has a pipelined design and cannot be clocked as
> slow as 100ksps without degrading performance
> - my CPU, the Atmel/Microchip XMega (selected for its peripherals, toolset
> support and familiarity for both me and my students) is an 8-bit AVR
> running at 30MHz and cannot directly process 10Msps
> 
> A simple D-flipflop based decimator was the easiest way to bridge this gap.
> The DMTD design has connectors for a (forthcoming) FPGA daughterboard to
> properly sinc-filter (and I/Q demodulate and...) the incoming samples.
> 
> Sincerely,
> 
> JD 'walk first, then run' B.
> 
> On Mon, Nov 4, 2019 at 6:38 PM W7SLS <w7sls.scott at gmail.com> wrote:
> 
> > Hello,
> >
> > (It has been a more few years since I designed / developed DSP for
> > spectrum analyzers for a major company, thanks for your patience.)
> >
> > I recall that:
> >
> >         sample @ fs -> decimate (toss samples) by a factor of N
> >
> > is equivalent to
> >
> >         sample @ fs / N
> >
> > If we wanted a lower sample rate, we would:
> >
> >         sample @ fs  -> lowpass filter at (say) 80% of (fs/2) / N ->
> > decimate
> >
> > Otherwise all of the energy > 50% of (fs / N) gets aliased into your data.
> >
> > Why not just sample at 100 kHz?
> >
> > What am I missing ?
> >
> > Thanks for considering,
> > Scott W7SLS
> >
> > > On Nov 3, 2019, at 12:59 PM, Jan-Derk Bakker <jdbakker at gmail.com> wrote:
> > >
> > > Is this not caused by the fact that I'm currently subsampling the ADC
> > > (conversion rate 10Msps, rate into the microcontroller 100ksps by
> > dropping
> > > 99 put of 100 samples)?
> >
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