[time-nuts] A simple sampling DMTD

[timeok at timeok.it]

Jan,

finally we begin to see something concrete.
I am not able to evaluate the performance of the noise floor that can be achieved but I would like to underline
that a very important factor is the repeatability and stability of the nf.

I would like to take this opportunity to thank TVB for the continuous stimulus he gives to this group of Time Nutters.

   Luciano

   timeok


   Da "time-nuts" time-nuts-bounces at lists.febo.com
   A "Discussion of precise time and frequency measurement" time-nuts at lists.febo.com
   Cc
   Data Sun, 1 Sep 2019 02:09:19 +0200
   Oggetto [time-nuts] A simple sampling DMTD
   Dear all,

   I've been working on a design for a (relatively) simple, standalone
   sampling DMTD. Very rough preliminary schematics can be found at
   http://www.lartmaker.nl/time-nuts/DMTD_rev0.99.pdf .

   Design goals are:
   - ps-level accuracy
   - comparison of frequencies between at least 10 and 50MHz, preferably
   between 1 and 100MHz
   - comparison of (selected) different frequencies (in my case: 10MHz vs
   50MHz)
   - standalone operation, field-portable
   - option for raw data sampling / (post)processing on a PC
   - option for generating a tuning voltage to lock the measured oscillator to
   the reference, so the DMTD can act as a PLL in phase noise test setups

   Context: you may remember that a year or two ago I posted to time-nuts
   about a GPSDO-design geared for mobile applications, which I was working on
   for an SDR-platform my students are working with. This SDR-platform has now
   grown to include a 100-channel phased array receiver. To validate the
   reference clock distribution in this array (amongst other things) I would
   like to have a DMTD. As the commercial offerings are outside the budget of
   our lab, I was planning to roll my own.

   The core of the system is a transformer-coupled LTC2140-14 dual 14-bit ADC,
   sampling at an offset frequency of nominally 10MHz+10Hz generated by a
   VCTCXO (with an option for an OCXO). The ADC was chosen for its large input
   bandwidth and small aperture jitter. Simulations of a simple software ZCD
   consisting of a digital filter and least-squares fitting showed that
   100ksps would be more than enough to get the desired accuracy. As the ADC
   design is unable to achieve sample rates lower than 1MSPS, D-flipflops are
   used to decimate the samples. These DFFs are also used to multiplex the
   2x14-bit samples to an 8-bit data bus going into one of the GPIO-ports of
   an XMega. The XMega runs the ZCD, and generates a tuning voltage for the
   offset oscillator. Communication to a logging PC is done with a
   galvanically isolated FT2232H, which has both an ASCII COM-port for the ZCD
   data and a control interface and an asynchronous FIFO to transfer raw
   samples. System power comes from the isolated USB bus or a barrel jack; BOM
   cost in qty10+ is around 100US$.

   (The DMTD has a few more power rails than I would have liked. Originally I
   had planned to use the LTC2295 and have a 3v3-only system, but after
   re-reading the NIST paper on SDR-as-a-DMTD I concluded that the single
   clocking path of the 2140 would likely have better aperture jitter
   correlation between the channels. As a 1.8V/10MHz XMega would only be
   borderline able to handle the computations, I ended up with this design.
   LVC logic is used to go from 3.3V->1.8V, LV1T translators for the opposite
   direction.)

   Design decisions and/or non-goals:
   - I considered putting a small FPGA (specifically a Lattice ice40
   UltraPlus) between the ADC and the processor. This was rejected because the
   performance of the decimator appeared to be sufficient, and I wasn't
   certain that I could get DDR mode + a CORDIC working in this FPGA.
   - Especially when I found the necessity to move part of the system to 1.8V
   I considered moving to an ARM. I stuck with the XMega as performance was
   sufficient, and I am very familiar with both the CPU and the peripherals
   (particularly time-stamping counters and the Event system) that would ease
   the ZCD implementation and issues like synchronization between processor
   and sampling system.
   - I looked into integrating a phase noise measurement, but could find no
   easy way that wouldn't degrade DMTD operation in the process. The tuning
   voltage output is an inexpensive compromise (as I still had a DAC and
   enough cycles to spare)
   - The main thing I'm unsure about is the effect of the balun on phase
   performance wrt temperature and termination matching. I've kept to the
   baluns as they add less noise than a fully differential amplifier would.

   While I've made this design for my own purposes, I would be more than happy
   to put it under an Open Hardware-license and/or work with TAPR or other
   parties to get it distributed, should there be interest.

   Thoughts?

   with kind regards,

   Jan-Derk Bakker
   [planning to start board layout tomorrow; looks like this should definitely
   fit on a 100x160mm Eurocard inside a Hammond 1455-series box]
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