[time-nuts] PCB layout question for GPSDO

[Tobias Pluess]

Sali Attila,

after I had read Mark's comments, I changed my layout quite a bit ;-) but more on that later.

Some comments for your comments. (Actually I should have sent the schematics as well! but I didn't because I was only concerned about the PCB.)

> D is usually used for diodes. For ICs and other complex parts
> usually U is used. In old German schematics, you could find often
> X for ICs. Connectors are usually X or J, depending on the faith
> you believe in. Quite often X is used for crystals too.
> Whatever you use, at least be consistent. Somewhere, there is
> a kind of "standard" (ie a document that lists what is kind of
> common) for naming components in schematics, but I can't find
> it at the moment.

not quite. Having D for diodes is maybe some US or whatever standard, but there is also an IEC and DIN standard. However, the newest version of it is very weird and not really useful (sorry, I have only a german link: https://de.wikipedia.org/wiki/EN_81346). At the time I learnt my job, the previous version of that standard was the https://de.wikipedia.org/wiki/DIN_40719-2 which I still use. (The new standard suggests using R even for diodes, and transistors may be R or Q, depending on their function, nonsense...). (Actually I just found out that I should have called my OCXOs G and not D :-)).


> FPC are not very hobbyist friendly, as they are usually only available
> in a limited number of wires and lenght combinations, with no way for most
> people to change their length. This might or might not be a problem with
> your circuit. Unless you need the density, I would avoid them.

You are maybe right, but I have a lot of those connectors here because I used them for another project a while ago where I made a little brushless motor controller, and those motors had such connectors. Maybe if I find a "nicer" connector I will use that, no big deal hear. I think it does not really matter, does it :-)

> You want to keep the antenna input as far away from the PPS signal as
> possible. The steep slopes that you want for the PPS output mean that it
> will be high in harmonic content. Depending on the exact type of D2, it
> could be harmonics up to 100MHz or it could be up to a few GHz.

D2 should be an 74ACT541 or 74AC541, depending on whether it is powered by 5 volts or by 3.3 volts (can be selected). Therefore, the slopes will indeed be quite steep. Maybe I will add another ground plane around the 1PPS. But I am afraid it is not really possible to move the 1PPS output to the other side, but maybe I can shift it closer to the OCXO (which I also don't really like...).

> That looks fine, though I would align the RF pins (see below: "E")

will do that, smart idea.

> What are the requirements on the power supply?
> With OCXO that can use up to 1.5A (Morion MV89), having a fuse is a
> good idea.

The OCXO takes min. 8 watts during the warmup phase and at least 2.5 watts when operating normally. Plus some margin. So the warmup current is some 700ish mA.

> You should not use the output of a switching supply to feed your antenna
> directly.

Yup, I already  changed that, because actually the power requirements on the 5 volt rail are not that high. I use now a linear regulator. Further, there is an LCR filter for the antenna. (But actually, I would expect that a commercial active antenna also has some filtering built-in in its power supply, doesn't it? at least it would make sense, but maybe to save some 1 or 2 cents, the manufacturers save every single resistor :-)).

> Make sure that you can disable the antenna monitor in software, otherwise
> your uBlox module will complain about no antenna being connected.

Yes, I checked that in the uBlox manual. Should be no problem. In fact my previous GPSDO design used the same module and there it didn't complain about the antenna. I don't have the manual at hand now, but as far as I remember, the active antenna monitor is disabled per default.

> No (see below: "J"). I guess ublox forgot to mention it, because by now
> most people should know it.

I wonder from where people should know that if they don't read this mailing list :-) because the uBlox manual really reads nothing about having traces under the modules. (However it does so for the older versions! maybe the newer modules are less sensitive to this?). But I learnt it now from this list and avoided all signals below the GPS module.
But it is not possible to avoid it completely; at least on the bottom layer I do have some signals (more on that later).

> Yes and no. Yes you should worry for all analog units that are suplied by it.
> No, the uC does not care.

Sure the uC doesn't care :-) for the active antenna and the OCXO I already changed to linear regs.

> Let me start with the simple things: Go for a 4 layer board.
> There is no excuse in not using 4 layers today, not for one-off
> projects. This will give you a full Vcc and a full GND layer
> in the middle which brings you lots of low-impedance ground and
> power supply goodness! Keep them unbroken, ie no wires on them and
> keep the vias far enough that they don't end up producing slits
> (small slits of 2-3 vias are ok).

This is actually 4 layers. I hid the centre two layers because otherwise one doesn't see a thing if they are visible. But I hate to route VCC and GND traces on 2layer boards, this is why I use most of the time 4 layers ;-)

> Then you almost always have only a single, large blocking capacitor.
> Unless you use some special capacitors (like the EMIFIL NF capacitors)
> that have a low associated inductance, you will have a very low
> self-resonance frequency of these capacitors, not to mention that
> there is a very wide spread. E.g. a 4.7µF 0603 capacitor will have
> a self-resonance frequency somewhere between 500kHz and 2MHz.
> Inductances are mostly package related, so within a series and at the
> same package size, the Inductance is constant, hence the self-resonance
> goes down with increasing capacitance. Inductance is also corrlated with
> size (roughly linear with length), so within a series and at same capacitance,
> the self-resonance frequency goes down with increased size. To battle this,
> people place small capacitance next to larger ones, such that the small
> capacitors provide the high frequency blocking and the larger ones the low
> frequency blocking. Be aware that beyond the self-resonance fequency,
> a capcitor acts as a inductor. Hence if the step between the small capacitor
> and the large capapcitor is too large, there might be a resonance frequency
> of the small capacitor C and the inductance L of the large capacitor. Usually
> steps of factor 10 are the largest you should do. Usually, for digital
> circuits, it's recommended to have a 100nF capacitor at each Vcc pin.
> For high speed parts that produce lots of high frequency components 10nF
> or even 1nF is recommended (in addition to the 100nF)
> The above mentioned EMIFIL NF are a big exception to this rule. Their
> construction makes it possible to use a single 4.7µF capacitor where
> traditionally you'd have a 100nF + 1µF + 4.7µF. See datasheet for details.

I only used 100nF X7R as blocking caps. Depending on the voltage, I used 0603 size on the 3.3V rail, 1206 on the 5V rail and 1210 on the 12V rail. This is because the capacitance is voltage dependent and the effect is smaller the larger the caps are.

> C: The trace of the antenna does not look like it's 50Ω... that's a bad idea
> too! According to my friends (who at that time were working at ublox), the
> most common cause for loss of sensitivity in their customers projects was
> the path from antenna connector to the module not being 50Ω and causing
> a lot of reflection. You also want to shield this trace from anything around
> it. I.e. place a row of thightly spaced vias to ground on both sides.

Actually, this trace is a 50 ohms microstrip. But for shielding reasons, I changed that now to a 50 ohms coplanar waveguide, which has lower losses and better shielding. Because the frequency is so low for GPS, I didn't want to make too many vias because it is simply not necessary I think. (Distance between two adjacent vias should be smaller than lambda/10 as a rule of thumb, which still gives some 10mm! so a via fence would be quite pointless I think?!).

> D: Your PPS driver gets its power over an R/C element. Yet that is one of
> the pieces that have the highes dynamic power on the whole board.
> The resistor will give you a voltage drop each time the driver switches.
> Depending on the exact value of R and the current, this can lead to marginal
> switching or chattering of the driver. It will definitively affect its
> output impedance. BTW: logic chips usually have an output impedance of 10-30Ω,
> which you have to account for when choosing the resistors for the 50Ω output.

you're right. However I plan to use 0R and a ferrite bead, but if I find out that phase noise or sensitivity is worse, I may change that. Besides that I have added some more serious blocking caps.

> E: OCXO like to have a constant 50Ω output impedance on their RF output.
> Going too far on either side will lead to harmonic contents, degraded
> frequency-pull stability and potentially other effects, if the internal
> isolation amplifier is not well designed. Also, you should ensure that
> you have no reflection, ie no impedance jumps or splits. If you want
> to split passively, use a lumped-element Wilkinson spliter or a resisitive
> splitter (adds another 3dB loss of power, ie output is -6dB instead of -3dB).
> As I wrote above, rotate the OCXO such that both RF pins are close as this
> is the most sensitive pin that is hard to control. The power supply can
> be easily stabilized by placing a capcitor close to the power pin (which you
> should do for both footprints). Similarly for the EFC.

You are for sure right, but on the other hand if we consider how short those stub traces are, I wouldn't bother too much. But Indeed I am considering adding a buffer stage between the OCXO and the rest to isolate the OCXO as much as possible from the remaining electronics.
Further, the clock for the microcontroller can be isolated by either some Schmitt trigger circuit or by a resistor, whatever works better. 

> E: Again the RC elements at the power supplies. Here with more complicated
> circuits, that can have more severe effects. I cannot judge the overall layout
> of the EFC circuit without seeing the schematics, but it looks like you have
> compromised proper routing of sensitive signals for compactness of the circuit.

Yes these are the power supplies for the OpAmps which are used as output drivers. R is 22 Ohms and C is 10u, giving some 700Hz corner frequency. The OpAmps supply current will of course give some voltage drop, but the 10u should keep the voltage quite stable and the PSRR will avoid having some funny modulations of the OpAmps.



OK I have attached the schematics. The only thing I have changed there is that I added an EEPROM which I will use to store some settings (i.e. PLL loop time constant, the last value of the DAC, maybe the GPS position?).

I also added the corrected PCB layout. It is 4 layers, but the two middle layers are hidden! The stackup is as follows

Top components
GND plane
VCC plane + 12V plane where applicable
Bottom routing + GND


Just for fun I also made a fancy 3D view (also added) :-).


Best
Tobias
HB9FSX



________________________________________
From: time-nuts [time-nuts-bounces at lists.febo.com] on behalf of Attila Kinali [attila at kinali.ch]
Sent: Monday, February 03, 2020 23:51
To: Discussion of precise time and frequency measurement
Subject: Re: [time-nuts] PCB layout question for GPSDO

On Thu, 30 Jan 2020 20:20:08 +0000
Tobias Pluess <tobias.pluess at xwmail.ch> wrote:

First a general note:

D is usually used for diodes. For ICs and other complex parts
usually U is used. In old German schematics, you could find often
X for ICs. Connectors are usually X or J, depending on the faith
you believe in. Quite often X is used for crystals too.
Whatever you use, at least be consistent. Somewhere, there is
a kind of "standard" (ie a document that lists what is kind of
common) for naming components in schematics, but I can't find
it at the moment.


> First I will explain a bit what is on the board.
> The connector X2 (top left) is a interface connector where I will connect a
> flat flexible cable to a front panel board, which is still to be made. In
> case the GPSDO will be mounted in a benchtop housing or so, one might want a
> front panel with some status display or even a set of buttons to change
> settings (e.g. change the PLL filter time constant).

FPC are not very hobbyist friendly, as they are usually only available
in a limited number of wires and lenght combinations, with no way for most
people to change their length. This might or might not be a problem with
your circuit. Unless you need the density, I would avoid them.


> Next to it are the SMA connectors for the antenna and for the 1PPS output,
> as well as two 10MHz outputs. The ICs N10 and N3 are output amplifiers which
> should provide some 40ish dB of isolation between the OCXO and the two
> outputs (such that the OCXO should not see it when a load is connected or
> disconnected).

You want to keep the antenna input as far away from the PPS signal as
possible. The steep slopes that you want for the PPS output mean that it
will be high in harmonic content. Depending on the exact type of D2, it
could be harmonics up to 100MHz or it could be up to a few GHz.


> D10 and D8 are two assembly variants which allow to install different OCXOs,
> I have currently planned to add an OSA 8663 OCXO. The DAC and filter stuff
> to control the EFC pin is on the right side.

That looks fine, though I would align the RF pins (see below: "E")


> The power supply, which is 15 volts, comes in at the lower left corner;
> there is a fuse (because the GPSDO will be left on basically forever, I
> think a fuse is a must, isn't it) and some large input filter cap.

What are the requirements on the power supply?
With OCXO that can use up to 1.5A (Morion MV89), having a fuse is a
good idea.


> To generate the 3.3 volts for the logic, a switching regulator (Traco TSR1)
> is used (N7); the regulator N9 generates 5 volts which is used for both the
> active antenna supply as well as the 1PPS output.

You should not use the output of a switching supply to feed your antenna
directly.


> The active antenna supply can be selected between 3.3 volts and 5 volts by
> means of a jumper.

Make sure that you can disable the antenna monitor in software, otherwise
your uBlox module will complain about no antenna being connected.

> My questions are the following:
> a) is it acceptable to route some signals under the GPS module? As one can
> see, the signals I have routed under the GPS module go to the front panel
> interface, i.e. they are not highspeed signals or so, but I still wonder
> whether you experts would worry about it (like "oh no, routing anything near
> the GPS module will disturb it and decreases its sensitivity" or something).

No (see below: "J"). I guess ublox forgot to mention it, because by now
most people should know it.

> b) would you worry about the switching regulators? I know linear would be
> better, but the professional GPSDOs also have switchers, and besides that a
> linear regulator would not be so nice because my power supply will be at
> least 15 volts.

Yes and no. Yes you should worry for all analog units that are suplied by it.
No, the uC does not care.


> c) is the usage of a RS232 chip a good idea or would you kick that out
> because they produce such massive amounts of EMI that it will disturb my GPS
> module or OCXO?

The way it is placed, I would care (see below for more details).


> d) is it a wise idea to use an LC filter for the OCXO power supply, or does
> this lead to another rabbit hole because the inductors will pick up magnetic
> fields (50 Hz...) and modulate the OCXO?

If the inductor is of a shielded type, then the induced voltage will be very
low. You can enhance that by placing the winding start (the dot on the
inductor) on the sensitive side, and the end of the winding where the
supply comes in. This way the outer layers of the inductor will shield
the inner layers. Though this is more a thing with higher frequency
EMI than at those low frequencies, and thus will not be effective
(though, the OCXO is also less sensitive to that).


> e) anything else important I forgot?

Quite a few bits, actually...

Let me start with the simple things: Go for a 4 layer board.
There is no excuse in not using 4 layers today, not for one-off
projects. This will give you a full Vcc and a full GND layer
in the middle which brings you lots of low-impedance ground and
power supply goodness! Keep them unbroken, ie no wires on them and
keep the vias far enough that they don't end up producing slits
(small slits of 2-3 vias are ok).

Your uC sits inbetween all the critical stuff. Which means it is close
to everything it shouldn't be close to. You should choose a different
arangement. Place the most noisy components at one side of the PCB, then
sort the rest by how sensitive they are and place them such. Route all
digital wires around the sensitive components. Be aware of return paths.
Read the four part series of Mark Fortunato on EDN on ground[1].
In general, you have way too few ground. Fill all non-used space with
ground and place GND-vias liberally everywhere. Make sure to not have
any antennas (pieces of ground plane that connected to the rest of GND only
why a single via at one end and "free floating" at the other)
A good ground is key to all low-noise circuits. For a small project
like this, I would not break the GND for the digital and analog parts.
Doing so correctly is not easy and often introduces more problems
than it solves.

Then you almost always have only a single, large blocking capacitor.
Unless you use some special capacitors (like the EMIFIL NF capacitors)
that have a low associated inductance, you will have a very low
self-resonance frequency of these capacitors, not to mention that
there is a very wide spread. E.g. a 4.7µF 0603 capacitor will have
a self-resonance frequency somewhere between 500kHz and 2MHz.
Inductances are mostly package related, so within a series and at the
same package size, the Inductance is constant, hence the self-resonance
goes down with increasing capacitance. Inductance is also corrlated with
size (roughly linear with length), so within a series and at same capacitance,
the self-resonance frequency goes down with increased size. To battle this,
people place small capacitance next to larger ones, such that the small
capacitors provide the high frequency blocking and the larger ones the low
frequency blocking. Be aware that beyond the self-resonance fequency,
a capcitor acts as a inductor. Hence if the step between the small capacitor
and the large capapcitor is too large, there might be a resonance frequency
of the small capacitor C and the inductance L of the large capacitor. Usually
steps of factor 10 are the largest you should do. Usually, for digital
circuits, it's recommended to have a 100nF capacitor at each Vcc pin.
For high speed parts that produce lots of high frequency components 10nF
or even 1nF is recommended (in addition to the 100nF)
The above mentioned EMIFIL NF are a big exception to this rule. Their
construction makes it possible to use a single 4.7µF capacitor where
traditionally you'd have a 100nF + 1µF + 4.7µF. See datasheet for details.


As for the PCB, I've attached an annotated version of your layout, so
I can point out a few things

A: Don't feed your antenna from a noisy power supply. You are comming
from a switched DC/DC with not enough filtering (especially at the lower
frequencies) and are on the way to the PPS driver chip. You will end up
with lots of spurs in the power supply that goes to the antenna which
in turn will lead to intermodulation products. Especially with cheaper
GPS antennas that have almost no power supply filtering or conditioning.

B: The trace that comes out of the ublox module is way too thin.
You have to be able to withstand short circuits for a short while
until the ublox internal short circuit detection triggers.

C: The trace of the antenna does not look like it's 50Ω... that's a bad idea
too! According to my friends (who at that time were working at ublox), the
most common cause for loss of sensitivity in their customers projects was
the path from antenna connector to the module not being 50Ω and causing
a lot of reflection. You also want to shield this trace from anything around
it. I.e. place a row of thightly spaced vias to ground on both sides.

D: Your PPS driver gets its power over an R/C element. Yet that is one of
the pieces that have the highes dynamic power on the whole board.
The resistor will give you a voltage drop each time the driver switches.
Depending on the exact value of R and the current, this can lead to marginal
switching or chattering of the driver. It will definitively affect its
output impedance. BTW: logic chips usually have an output impedance of 10-30Ω,
which you have to account for when choosing the resistors for the 50Ω output.


E: OCXO like to have a constant 50Ω output impedance on their RF output.
Going too far on either side will lead to harmonic contents, degraded
frequency-pull stability and potentially other effects, if the internal
isolation amplifier is not well designed. Also, you should ensure that
you have no reflection, ie no impedance jumps or splits. If you want
to split passively, use a lumped-element Wilkinson spliter or a resisitive
splitter (adds another 3dB loss of power, ie output is -6dB instead of -3dB).
As I wrote above, rotate the OCXO such that both RF pins are close as this
is the most sensitive pin that is hard to control. The power supply can
be easily stabilized by placing a capcitor close to the power pin (which you
should do for both footprints). Similarly for the EFC.

E: Again the RC elements at the power supplies. Here with more complicated
circuits, that can have more severe effects. I cannot judge the overall layout
of the EFC circuit without seeing the schematics, but it looks like you have
compromised proper routing of sensitive signals for compactness of the circuit.

F: Don't route digital signals below sensitive components. Keep them away from
all sensitive signals (here, EFC and RF). Best is, if you don't even cross
them. Ground guards help, if you have to route them closly, but this is more
a band-aid than proper engineering practice.

G: C58 is a Alu-Elko, which has a high inductance. If you use a good type
with low ESR it might cause a resonance loop together with C61+C62.
C61+C62+L6+C49 are a high Q resonator. Make sure its frequency is far away
from anything that could excite it.

H: You branch the power for the uC off from the power of the OCXO after
the filter. I.e. the spikes from the uC will be visible to the OCXO.
Branch the power at N8 instead.

I: Big capacitors at the power of the ublox module, while especially the RF
part is a high frequency component. Also use multiple vias to reduce the
inductance of the vias.

J: no digital wires beneath the RF part of the ublox. Yes, the M8T does
not specify that anymore, but I would still not do it. There is just too
much that can couple in. Unlike what Bob said, you don't care that much
about electrical coupling. The ublox modul has a pretty good ground plane
at the bottom, there is not much that will couple through that electrically.
But you care about magnetic coupling, which is not easily shielded by copper
planes. Ie even something 7 layers down with as many GND layers inbetween
might not be enough to reduce the magnetic coupling enought to be a non-issue.


As for power supply, I would go for a switched + LDO solution.
The DC/DC switched power supply keeps your losses low and the
LDO can clean up the noise of the switcher. If you choose a
switcher that works at 1-2MHz, then you will have an easy time
to filter out its noise. If you sync the switcher up to the 10MHz
signal, then you will make it allign properly and thus get out
of the way. Especially if you use 1MHz, then 10MHz is an even
harmonic, which means it will be even futher down. If it is
not synchronized, make the frequency such, that 10MHz lies
centered between two harmonics. I would not use LDO-replacement
switching regulators, as they might or might not be properly
designed. Rather design one yourself. The datasheets and
appnotes explain the procedure very vell and if you follow
the layout recommendations, you will be good (not using the
layout recommendation is the biggest mistake most people make
with DC/DC converters)


LM317 is a very poor choice for an LDO, even its
newer replacement part the LM1117 performs poorly in terms
of noise and regulation compared to more modern variants.
My recommendation are the TPS7A45xx series by Ti.
There are a few others, like LT1764 etc,
You don't have to go too crazy with the noise levels, as most
components are pretty resilient (OCXO included). The most
sensitive part will be your EFC circuit, but there you can
easily design it such, that the reference voltage source's
output noise will be dominating your noise. The PSNR is the
more important factor. If need be, add an active, high
frequency filter (e.g. a BJT with high f_t in an emitter
follower configuration with a fix drop) either before or
after the LDO.

HTH

Gruess und en schone Obig!

                        Attila Kinali



[1] https://www.edn.com/successful-pcb-grounding-with-mixed-signal-chips-part-1-principles-of-current-flow/


--
<JaberWorky>    The bad part of Zurich is where the degenerates
                throw DARK chocolate at you.
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