[time-nuts] DAC for OCXO disciplining

[Magnus Danielson]

Hi Hal,

On 2020-01-18 22:50, Hal Murray wrote:
> magnus at rubidium.se said:
>> I was amazed that it was this simple to move energy to where it makes less
>> damage. Turns out that FPGA logic wise, it's at the same cost as PWM. 
> You can do the same thing in software.  Many small CPUs have IO gear that lets 
> you send raw bits.  Just setup a buffer in memory and send it out.
>
> Simple UARTs aren't ideal due to start/stop bits but you can probably work 
> around that.  Your output range is 10% to 90% rather than 0-100.  Many serial 
> ports have modes without start/stop bits.  I haven't looked carefully but some 
> of the gear for simple 2 or 3 wire protocols may work.
>
Sure, you can do this in CPU, but you want to make the updates fairly
well spread over time, with relatively robust timing, which you for sure
can do, the PICDIV shows this, but you need to know this is part of the
design problem and focus on that.

I implemented it in FPGA because I was already doing it in the FPGA
domain, and getting stable enough timing was trivial and would still be
my preferred method.

Cheers,
Magnus