[time-nuts] Odd-order multiplication of CMOS-output OCXO

ew ewkehren at aol.com
Sun Jan 19 11:45:08 UTC 2020


The easiest way to do it is with an ICS 512 or ICS 570. We use the 570 all the time
Bert Kehren
In a message dated 1/18/2020 7:34:00 PM Eastern Standard Time, mark at hau.nz writes:

Hi time nuts,
I'm looking for a 5x frequency multiplication scheme to let me use a16-MHz square-wave OCXO for an ADC encode clock at 80 MHz.
Constraints in order of importance:
1. Don't degrade the nice phase noise of the OCXO (-90 @ 1, -120 @10,-140 @ 100, -160 @ 1k) any more than necessary; at the very least, itshould not impact the ADC noise floor in the primary 0-40 MHz image.
(This should give quite a bit of leeway, but better is better :)
2. OCXO power consumption (~150 mW) should still dominate totalclock-system power.  Would like to keep the multiplier/buffer under 50 mW.
3. No supply rail above 3.3V.
This "ought to be" (?) easy, because the OCXO output is already rich inodd harmonics.  All that's needed is to isolate and perhaps buffer theright one without screwing up my noise spec.  This is where I could usesome help...
The ADC (AD9266) wants a differential clock, sinusoidal or squaredoesn't matter.  The datasheet recommends transformer coupling withantiparallel diodes to keep the swing ~ 1.5Vp-p.  (The min/max spec saysanything between 0.2 and 3.6V.)   The 3.3V OCXO should give me 0.8Vp-pat the 5th harmonic without any amplification, so in theory I guess Icould just filter and transformer couple and be on my way.  But perhapssome amplification is in order to increase the slew rate?
I looked at the Wenzel tech notes for ideas, e.g. this one using logicgates and tuned circuits:http://www.techlib.com/files/hcmos.pdfbut I lack the background to evaluate the pros and cons of introducingextra CMOS logic.
I also found this common-base amp circuit in the archives:https://www.febo.com/pipermail/time-nuts/2016-January/095683.html  andhttps://www.febo.com/pipermail/time-nuts/attachments/20160126/ae3b4be8/attachment-0001.pdf
I've read that I should avoid high-Q tuned circuits, because they willintroduce more noise with temperature variation.  Are there any rules ofthumb for how much Q is too much?
Any pointers would be most appreciated!
Thanks,Mark


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