[time-nuts] Odd-order multiplication of CMOS-output OCXO

[Mark Haun]

Hi Bob,

On Sun, 19 Jan 2020 09:37:39 -0500
Bob kb8tq <kb8tq at n1k.org> wrote:
> Is your intended application tolerant of spurs at 16 and 32 MHz? If
> not, do they need to be in the 90 dB down vicinity (= the SFDR of the
> ADC) ?

I guess you mean stray coupling between the oscillator, clock
conditioning circuitry and the analog inputs?  (Spurs on the ADC clock
input shouldn't matter as long as the zero crossings are clean and
jitter is low.)

This would be for a direct-sampling HF (shortwave) radio.  A few extra
spurs are OK, especially synchronous ones like these which you could
theoretically subtract in the digital domain.

Regards,
Mark

> > On Jan 18, 2020, at 7:33 PM, Mark Haun <mark at hau.nz> wrote:
> > 
> > Hi time nuts,
> > 
> > I'm looking for a 5x frequency multiplication scheme to let me use a
> > 16-MHz square-wave OCXO for an ADC encode clock at 80 MHz.
> > 
> > Constraints in order of importance:
> > 
> > 1. Don't degrade the nice phase noise of the OCXO (-90 @ 1, -120
> > @10, -140 @ 100, -160 @ 1k) any more than necessary; at the very
> > least, it should not impact the ADC noise floor in the primary 0-40
> > MHz image. (This should give quite a bit of leeway, but better is
> > better :)
> > 
> > 2. OCXO power consumption (~150 mW) should still dominate total
> > clock-system power.  Would like to keep the multiplier/buffer under
> > 50 mW.
> > 
> > 3. No supply rail above 3.3V.
> > 
> > This "ought to be" (?) easy, because the OCXO output is already
> > rich in odd harmonics.  All that's needed is to isolate and perhaps
> > buffer the right one without screwing up my noise spec.  This is
> > where I could use some help...
> > 
> > The ADC (AD9266) wants a differential clock, sinusoidal or square
> > doesn't matter.  The datasheet recommends transformer coupling with
> > antiparallel diodes to keep the swing ~ 1.5Vp-p.  (The min/max spec
> > says anything between 0.2 and 3.6V.)   The 3.3V OCXO should give me
> > 0.8Vp-p at the 5th harmonic without any amplification, so in theory
> > I guess I could just filter and transformer couple and be on my
> > way.  But perhaps some amplification is in order to increase the
> > slew rate?
> > 
> > I looked at the Wenzel tech notes for ideas, e.g. this one using
> > logic gates and tuned circuits:
> > http://www.techlib.com/files/hcmos.pdf
> > but I lack the background to evaluate the pros and cons of
> > introducing extra CMOS logic.
> > 
> > I also found this common-base amp circuit in the archives:
> > https://www.febo.com/pipermail/time-nuts/2016-January/095683.html
> > and
> > https://www.febo.com/pipermail/time-nuts/attachments/20160126/ae3b4be8/attachment-0001.pdf
> > 
> > I've read that I should avoid high-Q tuned circuits, because they
> > will introduce more noise with temperature variation.  Are there
> > any rules of thumb for how much Q is too much?
> > 
> > Any pointers would be most appreciated!
> > 
> > Thanks,
> > Mark