[time-nuts] Odd-order multiplication of CMOS-output OCXO

[Mark Haun]

On Mon, 20 Jan 2020 16:34:08 -0800
jimlux <jimlux at earthlink.net> wrote:
> On 1/20/20 3:40 PM, Mark Haun wrote:
> > On Mon, 20 Jan 2020 17:31:51 -0500
> > Bob kb8tq <kb8tq at n1k.org> wrote:
> >
> > Unfortunately I suspect the added digital power consumption in the
> > FPGA would be greater than the analog power for a PLL solution.  As
> > much as it pains me to say that as a DSP guy ;)  I need to think
> > about this some more, though.
> 
> Many (big) FPGAs these days have power consumption dominated by the 
> leakage current of all the gates. Even going back as far as the
> Virtex 4, the dependence of power on clock rate and number of gates
> toggling is pretty small.
> 
> I've not checked something like a Zynq.

This is why I'm targeting a small-ish Spartan 7, probably XC7S25.
Datasheet quiescent current on all supplies is on the order of 70 mW.
Pretty impressive when compared with only a couple of generations ago.
And even this small FPGA gives you 80 DSP blocks and 1.6 Mbits of block
RAM.

Mark