[time-nuts] Odd-order multiplication of CMOS-output OCXO

[Mark Haun]

On Wed, 22 Jan 2020 00:30:12 +0100
Magnus Danielson <magnus at rubidium.se> wrote:
> On 2020-01-21 19:41, Mark Haun wrote:
> > What are the adverse consequences of using large divisors in the
> > loop, as would be required for my odd OCXO frequency?  E.g. on
> > paper, it would seem that I could use 80 MHz / 625 = 16.384 MHz /
> > 128 = 128 kHz PFD frequency.  How would this differ from a more
> > "normal" ref clock frequency of 10 or 16 MHz with smaller divisors?
> 
> From my experience, such factors and rate of phase comparator is
> relatively easy to work with and get to work reasonably well for most
> purposes. I recommend you to use a PI-loop.
> 
> For a step-up you want to keep the PLL bandwidth fairly large, and
> that helps making it easy.

FWIW, here (attached) is the best result I obtained from ADISimPLL
for locking an 80-MHz VCXO (Abracon ABLNO) to a 16.384-MHz OCXO
reference.  This uses the ADF4002 with a loop bandwidth of only 40 Hz;
larger than that and it says the ADF4002 noise is affecting the result.
Also, the tool is quite limited in how you specify phase noise of the
reference and VCO, so I couldn't quite get the reference noise to match
the datasheet plot---it should be better than what is shown.  The VCXO
noise is pretty close though.

Mark
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