[time-nuts] New Subscriber, DIY GPSDO project (yes, another one)

[Matthias Welwarsky]

Hi Attila,

thanks for the review, but I think you're a bit too pessimistic about the 
power consumption. But let's get through your points:

On Samstag, 29. Februar 2020 20:08:13 CET Attila Kinali wrote:
> 
> First of all, the power supply seems to be under-dimensioned.
> You are going down from 24V, which means you are burning around 7
> times the power consumption of your electronics in the LDOs.
> Even if you assume everything is low power and the electronics only
> use around 200-300mW, that means you burn another 1.4-2.1W (Watt, no milli!)
> in the LDOs. Something in the order of 500-700mW consumption in the
> electronics would be probably closer to the truth. I.e. you should plan for
> ~4W that are dissipated by the LDOs. Or better still,
> calculate how much power each component uses and design the power
> supply accordingly.

I'll check the total power consumption when I assemble the next two PCBs, but 
I think you're probably not far off. The bulk of it is however the Ublox 
module, definitely the single most prominent consumer.

> The bulk (ie a bit less than half) of the power is dissipated in U3,
> which is a 0.5A spec'ed LDO in D3PAK... if it's properly cooled.
> Your PCB doesn't show any heatsink and will dissipate into the board.
> Assuming that you can dump more than 100-200mW at a single spot
> into a densly populated PCB without some thermal design is asking
> for trouble. You will need a heatsink. If we are going by the above
> 4W number, you need to get rid of at least 2W in U3. Assuming a
> 20°C above ambient case temp is ok, this means a maximum thermal
> resistance of 10K/W, better 5K/W. That's doable with a large D3PAK
> heatsink, but even that is probably pushing it, unless you add a fan

No heatsink, just a couple of thermal vias into the ground plane and it gets a 
bit warm, but not more than 35°C (case temperature). I just checked with a 
thermocouple. 

> The next problem is U12. I don't know which one of the ublox
> modules you choose, but be warned: they consume a lot of power!
> At the lower end of the spectrum we have the power safe mode
> of an NEO-6 spec'ed at typically (not max!) 11mA during tracking.
> It can, and will go up to 47mA(typ) during aquisition. Max
> current consumption is spec'ed at 67mA. The LEA/NEO-M8T are
> spec'ed at 32mA average, 67mA max. A LEA-5 is known to go up to
> 180mA during aquisition, while the datasheet only says only
> 150mA max. And all this is not yet including the antenna power
> supply, which is another 10-30mA. So, assuming you have a modern
> ublox module, you are in for around 100mA current consumption
> during aquisition (can last for several minutes) and around 50mA
> during tracking. That means poor little U12 has to dissipate 2W
> during aquisition and 1W during tracking. There is no way a tiny
> SC-73/SOT-223 case is going to handle that.

Yep, this one was more of an afterthought when I realized that I couldn't 
route the 12V rail through to the Ublox module and that the 12V regulator 
would never be able to cope with the additional load thermally. So I decided 
to put another 5V regulator in front of the Ublox module and pray. It keeps 
thermal equilibrium of around 46°C when the receiver is in HOLD mode, but 
certainly gets pretty toasty while it's acquiring satellites. If I do a 
revision, I'm definitely going to put a buck converter here, there's some 
pretty nice synchronous designs from TI with very good efficiency.

> The next two LDO, U4 isn't any better off. It comes in even
> tinier SOT-23-5 cases, which I wouldn't trust beyond 100mW
> dissipation. That limits the current going through it to
> about 10mA. Yet there are quite a few components on it that
> definitely draw more alone. Heck, U8 alone probably draws 40-50mA.
> Guestimating, I would say there is a total 60-100mA on U4,
> which would result in something around 0.5-0.8W of dissipated power.

Yes, but you're overestimating the power consumption. The complete digital 
part has no more than, say 30mA total consumption on the 3.3V rail. U4 gets a 
bit warm, but 40°C case temperature is OK'ish. Still a lot, but apparently the 
thermal conductivity is enough. However - this is with no load on the 10MHz 
output. The output driver is connected to the same power rail. This might push 
U4 over the edge ;)

Keep in mind also that the ambient temperature is not 20°C, the whole PCB sits 
in front of the LPRO-101 with a surface temperature of about 40°C. 

> Only U9 and U10 have low enough loads that I would say that they
> can do their job. Though you should calculate the maximum load
> and dissipated power, just to be sure

These two are fine, they don't need source a lot of current. 

> I would also recommed using a DC/DC switched power supply to go
> down from 24V to 5V, to get around the big bulk of waste heat
> production.

For the GPS pre-regulator definitely. For the rest of the electronics - maybe. 
But I wanted the power supply of U6 at more than 5V and I had to balance the 
power dissipation somewhat to not burden everything onto U3, hence the 12V 
intermediate voltage. Still, U3 could be replaced by a buck converter down to, 
say, 6V, that would take the stress off of all downstream LDOs. I just need to 
find something that has an appropriate footprint. I don't have a lot of PCB 
area. I seem to remember that synchronous buck converters can be had in 
SOT-23-6 package ;) I just need to find something with a high enough switching 
frequency so that the inductor can be very small.

> Going forward.. or rather backward. You have Q1 presumably as
> reverse polarity protection. Unfortunately it doesn't work that
> way. The way you put the FET in, it will act as a source follower.
> Meaning the voltage at the source will be the voltage at the
> gate minus the threshold voltage. Now the gate is being pulled
> up by a 8.4V Zener diode, which means the gate is supposedly
> 8.4V-ish below the source, but that's more than the thresold
> voltage, so the FET closes off and doesn't conduct. For this
> kind of thing to work, you would have to turn the FET around,
> the source pointing at the power source. But then, while
> the FET sure does not conduct during reverse polarity,
> the body/protection diode of the FET will conduct. Hence you
> don't get any protection there. It would be a better idea
> to just use a 1N4001 instead. Simpler, and can withstand
> 100V reverse polarity :-) D4/D5 are probably meant as over
> voltage protection. While this definitely works, it's kind of
> crude. At least at these voltages. If this would be a 1kV system,
> then using a triac would be fine, but for low voltage electronics,
> the time it takes to fire a triac and get it switching will not
> prevent the downstream electronics from getting fried. A better
> approach is to use an appropriately rated TVS diode. Overall
> simpler and better (aka faster) protection.

You probably missed that Q1 is a p-channel mosfet. The circuit around Q1 is 
basically a textbook approach to reverse polarity protection. If you google 
for the term "reverse polarity p-channel mosfet", this is what you find. With 
a bit of effort I could probably find it in the "Art Of Electronics" I have on 
my desk: The idea is to have the body diode source the initial current until 
the source voltage raises above the threshold voltage to switch the FET on. In 
reverse polarity, the diode will not conduct and the FET will stay off. The 
Zener is only to limit the gate-source voltage to around 10V.

On the idea of using a TVS diode instead of the SCR crowbar - forget it. I 
tried. By the time the polyfuse trips, the TVS has released the magic smoke. 
The LPRO-101 draws about 1.7A during initial heat-up, the fuse has to be rated 
accordingly. A TVS diode with a breakdown voltage of 27V would have to 
dissipate, say, about 50 Watts for a couple of seconds at least. I used a 
LDP24A, Besides from being of enormous size, I didn't trust it not causing a 
fire when the protection trips.

> Going further back: You use two decade counters to devide the 10MHz
> signal from the rubidium by 2000. and use this than as a stop signal
> for the TD7200. Yes, this idea works but be aware that the 74390 is
> a ripple counter. This means that each division stage is clocked by
> the previous stage. This means the jitter of each stage add up. If
> you want to stay with this topology, I would suggest switching to
> two 74161/74163 which are synchronus counters. I would also suggest
> that you go further down in frequency than 500kHz. With 500kHz you
> only have a 2µs window within which you can alias free determine
> the phase. If you ever have any GPS outage, +-1µs phase drift is
> accumlated quickly in just a few hours, even with a rubidium. Of
> course, If you don't mind that you have phase discontinuity during
> outages, that's fine.

Yep, that's a good idea. Though, holdover stability wasn't really a design 
goal - yet. I simply didn't consider what would happen when the GPS coverage 
returns after a prolonged outage. So, yes, TIC could wrap meanwhile. But since 
I don't output a 1PPS signal, maybe I wouldn't care.

> If you don't mind going to another architecture, I would suggest
> to use a half-Nutt interpolator and timestamp the PPS pulse. Then
> you can use the timer unit of your µC to do the coarse counting.
> Tobias' and my GPSDO design both do that. There are two advantages
> for doing this: 1) You have a shorter measurement window of <200ns,
> which in which the TDC7200 is better than 100ps accuracy (typical
> better than 60ps). 2) You don't get any problems with measurement
> windows as you have absolute timestamps.

I actually tested the TIC circuitry stand-alone with a coherent start/stop 
(sourced from the same reference clock) and the performance was fine. Standard 
deviation of less than 30ps over 1000 measurements or so. The 56ps granularity 
of the TDC7200 was clearly visible in the results. Anyway, 100ps is better 
than necessary. I did a couple of tests with the GPSDO simulator on 
Leapsecond.com, resolution below 1ns or so didn't (seem to?) make a huge 
difference on the performance. If you look at what a GPS receiver typically 
delivers, you'll need to average over many, many, many seconds anyway ;)

Using the TDC7200 in mode 2 seems to be "good enough".

> Overall, I would recommend you have a look at Tobias Plüss' schematic.
> He has done a very nice job for the design. Another very good
> example is Nick Sayer's GPSDO, which is not only well made, it's
> one of the most simple designs out there, while still reaching
> very good performance (the only two simpler designs, I am aware
> of, are the ones by Brooks Shera and James Miller).

The G3RUH GPSDO is indeed very simple. Basically an XOR PLL with a very tight 
loop bandwidth. Brooks Shera I don't know yet, but the one by Nick Sayer is an 
analog interpolator with a 4046 as a phase discriminator switching a FET 
charging a capacitor feeding an ADC. Similar to Lars Walenius' GPSDO. That 
design is even a bit simpler than the one from Nick Sayer.

Do you have some schematics online of your design? I've seen Tobias schematics 
on the list, but I only looked at the last month of postings so far.

Best regards,
Matthias

> 
> 
> 			Attila Kinali