[time-nuts] New Subscriber, DIY GPSDO project (yes, another one)

[Matthias Welwarsky]

On Dienstag, 3. März 2020 18:41:43 CET Attila Kinali wrote:
> On Tue, 03 Mar 2020 14:42:49 +0100
> 
> Matthias Welwarsky <time-nuts at welwarsky.de> wrote:
> > In the meantime, I'm thinking of another modification to make: getting rid
> > of the HC390 ripple counter. I think I might be able to use the STM32 as
> > a frequency divider. I just have to figure out how to program the timers.
> > What might work is the following:
> > 
> > - Feed the 10MHz clock into the external trigger input for the timer,
> > configure the timer to count the trigger pulses instead of the internal
> > clock  source.
> 
> Better idea: feed the 10MHz input directly into the clock input
> RCC_OSC_IN and let the STM32 derive its internal clock from that.
> Doing that, the clock of your timer unit will be phase locked to
> the 10MHz signal. Then you can use the timer for both capturing
> the incomming PPS and for generating the 250kHz. The capturing
> will solve the issue with aliasing. The timer output should have
> a jitter in the low ps range. There is a bit more going on than
> you would want in the STM32 for a low noise signal, but most
> likely not so much as to degrade the output enough to matter.
> If you are worried about that, you can still add a 7474, with
> D connected to the STM32 timer output and the CLK to the 10MHz
> to clean the jitter. But as I said, that's probably not necessary
> in this case.

I have an STM32F042 without FPU and I'm doing a lot of double precision math. 
I'm not sure I can spare the 4/5th of the cycles.

> 
> If you want to create a stabilized output PPS from the STM32,
> you will need to do some software trickery to align the PPS,
> as you cannot hope to shift the phase of the Rb in a reasonable
> time to match up.

That's not very high on my laundry list.

> 
> 			Attila Kinali