[time-nuts] new WWVB BPSK dev board

[John Moran, Scawby Design]

Good morning

I agree that 1deg is overkill but I was simply extrapolating one extra decade from BOB kb8tq's "backing off a bit" comment where he got down to 10deg. :-)

10MHz is an obvious sample rate - sorry, that fell into a blind spot here!

I think I will get distracted over Christmas sketching out some designs ...

Thanks - John

-----Original Message-----
From: Poul-Henning Kamp [mailto:phk at phk.freebsd.dk]
Sent: 4 December, 2018 11:03 PM
To: Discussion of precise time and frequency measurement <time-nuts at lists.febo.com>; John Moran, Scawby Design <john at scawbydesign.co.uk>
Subject: Re: [time-nuts] new WWVB BPSK dev board

--------
In message <AM0PR03MB4129FBD0922805FC14B8CEFDE4AF0 at AM0PR03MB4129.eurprd03.prod.outlook.com<mailto:AM0PR03MB4129FBD0922805FC14B8CEFDE4AF0 at AM0PR03MB4129.eurprd03.prod.outlook.com>>, "John Moran, Scawby Design"
 writes:

>However, fast A-Ds are not particularly cheap and you would need circa
>50MHz sample rate to resolve 1deg of the carrier, and TVB has already
>stated that there are no time benefits to BPSK, so this is all just an
>interesting technical exercise, isn't it?

I admit it would be interesting to do the allan variance on it, but measuring the carrier to 1 degree in every single cycle is waaaaay overkill.

1 MHz sampling rate is fine, but go for 5 or 10 MHz so you can drive the ADC directly from your house-standard.

And BPSK *does* improve the timing, because you can very precisely measure when the change of phase happens, and it since it happens at a carrier zero-crossing you can filter it down to +/- sample.

--
Poul-Henning Kamp       | UNIX since Zilog Zeus 3.20
phk at FreeBSD.ORG<mailto:phk at FreeBSD.ORG>         | TCP/IP since RFC 956
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