[time-nuts] Modern signal generators

[Gerhard Hoffmann]

Am 11.12.18 um 20:30 schrieb jimlux:
> On 12/11/18 10:23 AM, Richard (Rick) Karlquist wrote:
>>
>>
>> On 12/11/2018 9:13 AM, djl wrote:
>>> Rick: I've spent some time with the dds blocks. We found them to 
>>> generate lots of low level spurs, making lots of "birdies" when used 
>>> as local oscillators in receivers.
>>> We had better results using:
>>> https://www.silabs.com/products/timing/oscillators.
>>>
>>
>> I was talking about making a programmable frequency synthesizer
>> with a DDS, to use as a general purpose signal generator.
>>
>> A silabs part functions exactly the same as a crystal oscillator
>> once it receives its one-time programming at the factory, AFAIK.
>>
>
> Most of the Silabs parts are available in an  I2C programmable version 
> rather than the factory programmed flavor.
>
Yes, but they all have in common that their oh! so good jitter values

exclude the first 12 or even 50 KHz from the carrier. With enough DSP

you can shove a lot of dirt towards the first 12 KHz: look, ma, no birdies.

Those without an E5052B or FSUP won't notice, and the OC-48 or OC-192

or other telecom target market won't care anyway. But the birdies are not

magically gone, they were squashed under the DSP steam roller.


The nagging DDS birdies happen when you are close, but not exactly on

a subharmonic of the clock frequency. In an avionics com transceiver I got

easily rid of them by using 2 clock frequencies and switching as best

for the channel. With this DO-178? stuff you are punished for oscillator

birdies when you try to make the receiver more sensitive. :-(


Ulrich and DJ7VY and some others have shown us >40 years ago how to

do shortwave/VHF receivers (hey, I was still in school then, and it gave me

the kick towards RF engineering) and ring mixers still have their place, but

not in the input of a ham rig. There should be a 16 bit 150MHz+ ADC after

the tuned preselector, and the rest is digital. I have published a

synthesiseable sine / cos table on opencores.org a decade ago. The test

bed is a DDS. just fill in the resolution you want and buy an el cheapo 
Xilinx

Spartan FPGA to give it a home, and then filter & decimate the hell out of

your ADC data. No more analog LO. We now have things like AD9172,

ADC12J4000 and AD9625 to play with. That's the new frontier.


Now that I have your attention.... I'm currently interested into 1/f noise,

or, more precisely, in how to avoid it. Is there anything known on 1/f

in FETs as used in switches, such as choppers? Is there more than thermal

noise of the channel? There is a paper of the Univ of Twente that 
suggests there

is some time delay when fets are turned on until the trap locations turn 
active.

That could be a nice by-effect.

Even van der Ziel and Cobbold are silent about that.


cheers,

Gerhard, DK4XP