[time-nuts] Quadrature Phase Noise Measurement

[Gerhard Hoffmann]

Am 12.10.19 um 07:23 schrieb John Miles:
>
> The next step up from that would probably be the Red Pitaya.  Marco Gottardo
> has a book called (literally) "FPGA to High Speed ADC Data Streaming," which
> explores various data acquisition applications with the Red Pitaya including
> baseband noise measurement.  I have a copy of this one that I haven't had
> time to look over in depth.  The English is a bit rough in places, but the
> content seems worthwhile for anyone contemplating a Zynq-based digitizer.
>
> None of these options will bring data directly into PN.EXE, of course.  But
> that's the easy part of the exercise compared to the general problem of data
> acquisition.


I have a digitizer project on the back burner. It consists of a

$55 Beaglebone Black and 2 stamp-sized boards. The BBB is a

credit card sized single board computer featuring a 1 GHz ARM processor

with NEON floating point, 512 MB RAM, LAN interface & running Debian Linux.

It also has 2 PRUs; these are 200 MHz controllers without pipelining, 
intended

to do the dirty real-time work. There is shared RAM between the PRUs and

the ARM. The PRUs have fast access to selected IO pins and some devices.

It is possible to place edges with 5 ns resolution at the pins in software.


All software development is self-hosted, including the gcc and the 
C-compiler

for the PRUs. All you need is either a terminal program or ssh on a 
computer

with a display / keyboard.


The ADC I have selected is the LTC2500-32. It has built-in 
filters/decimators

so it can go to really low frequencies; that's needed here because my 
Agilent

89441A is bad there. Sample rate is 1 MHz at 24 bits.

< 
https://www.digikey.de/product-detail/de/linear-technology-analog-devices/LTC2500CDKD-32-PBF/LTC2500CDKD-32-PBF-ND/6670442 
 >

The stamp sized board has the ADC, the recommended differential driver,

2* LT3042 for analog & digital VCC, low drop regulator for driver VEE 
and the

LTC6655 low noise reference. Output is SPI @ 100 MHz, needed to avoid

digital action in the sampling window at 1MSPS.


The CPLD stamp has a tiny Coolrunner2 to divide the sample rate from the 100

MHz oscillator and to read the 100 MHz SPI from the ADC and pass it 
byte-wide

to the Beaglebone. The BBB has enough IO bandwidth for 3 ADCs; with some

effort 4 should be possible. Enough for a 3 cornered hat.


State of the software is now: ARM can start PRU programs, setup the ADC,

the PRU can read the ADC output and put it into the shared RAM. The ARM

can read/write the shared RAM.


There is a command interpreter between ARM and PRU and the ARM can read

the results. I was able to compile the Fastest FFT in the West (FFTW) on 
the ARM.

The LAN interface between the ARM and the laptop works much like the 
Agilent

89441A. No need to re-invent the wheel. You simply open port 5025 on 
192.168.x.y

and write then GPIB-like commands and read the results. No GPIB dongles.

There is a command interpreter on the Linux side that recognizes simple 
commands

and answers them.


Programs, circuits, Altium Designer files and VHDL for Xilinx ISE are 
available

under BSD or GNU copyleft. A good part of the effort was to throw away

outdated documentation and to get a tool set that works together, finding

the right addresses, PRU / ARM communication etc.


I probably won't have much time to continue with this until the xmas season,

but that is approaching fast.


I also have a Red Pitaya. It would require modifications for base band

operation and the hardware is not really open. The 3 cornered hat would

require 2 of them & synchronization.


regards, Gerhard









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