[time-nuts] A simple sampling DMTD

[Attila Kinali]

Hoi Jan-Derk,

As I am late to the party, I take the liberty to answer a few mails together

On Sun, 1 Sep 2019 02:09:19 +0200
Jan-Derk Bakker <jdbakker at gmail.com> wrote:

> I've been working on a design for a (relatively) simple, standalone
> sampling DMTD. Very rough preliminary schematics can be found at
> http://www.lartmaker.nl/time-nuts/DMTD_rev0.99.pdf .

The design is quite decent and I don't see anything "obviously wrong". ;-)
The choice of the LTC2140 is good, there might be better options in
terms of noise, but the LTC2140 is good and available at a decent price.

The biggest change I would make, would be to use a higher sampling
frequency and use an FPGA with a CORDIC as phase detector. Especially
as your goal is to measure the phase difference of a distribution system,
where the frequency of both inputs is exactly the same.

The reason for this is rather simple. You are using a LMS fit over
32 samples around the zero crossing of a 10Hz signal with a ~10MHz
sampling clock. This means you have just a few samples over what would
be otherwise possible. A CORDIC does cover the whole sine wave. While 
this does not give you n-times as many samples, it improves the SNR quite
considerably. I don't have exact numbers for how much, as I haven't
had the time to go through the math for this, yet.
The other advantage is, that you operate close to the 1/f corner frequency,
Ie the effect of 1/f noise hits you (almost) fully. Sampling the full
sine wave instead gives you the ability to work far away from the 1/f
corner and thus greatly reduces the effect of 1/f noise.

If you are interested, I have a parametrizable CORDIC core written
in VHDL ready for use. At the low sampling frequencies the LTC2140
works, a MAX10 would be already more than good enough. It probably
should be able to support even higher sampling frequencies in the
order of 100MHz (haven't synthesized it for a MAX10, but guesstimating
from the datasheet). The FPGA could also do the (digital) filtering
and down-sampling, so your uC wouldn't have to do any expensive
calculations.

As sampling period I would choose something that is such that the
signal ends up approximately centered within a niquist zone, but
with an as odd ratio as possible. Ie the reduced fraction a/b should
have as large a and b as possible. The reason for this comes from
number theory and the way how spurs form in DDS. 
Alternatively, but with a higher effort, one can choose the sampling
rate such, that a/b has small a and b. This will result in a lot of
the spur energy to fall onto the signal and by that reduce the noise
floor which is mostly spur generated for this kind of application.
The difficulty lies here in having a sampling source that is locked to
the signal but has as low noise as possible, as the close in noise
of the sampling source now defines how well the spurs match up with
the passband signal. Again, I cannot say exactly how much better this
would be, as I haven't gone through the math yet.


On Sat, 5 Oct 2019 20:49:50 +0200
Jan-Derk Bakker <jdbakker at gmail.com> wrote:

> I've been running some tests with a 10MHz sine wave from an Abracon AOCJY1
> OCXO into a resistive divider, feeding both channels of the DMTD through
> identical SMA cables (Amphenol 135101-07-M0.50). At the ADC input this
> yields a -12dBFS sine wave (PSD of the beat note:
> http://www.lartmaker.nl/time-nuts/PSD%20of%20AOCJY1%20into%20the%20LTC2140.pdf
> ). Over a 34000s measurement period the ZCD as described upthread (least
> squares fitting of the 32 samples nearest the zero crossing of the rising
> flank, but without DC/drift correction) shows a time difference of 6.3ps
> between the two channels, with a standard deviation of 1.6ps (full plot:
> http://www.lartmaker.nl/time-nuts/DMTD%20Time%20between%20zero%20crossings%20with%20resistive%20divider%20(no%20offset%20correction).pdf
> ).

I am a bit astonished by the high noise level you have. I would have expected
this to yield something below 1ps, judging from what we got from what Nicolas
acheived in his work on the sine exitation based TIC[1]. The apperture jitter
of the LTC2140 is spec'ed with 100fs, so that should be the first limit
to run against. Though, based on Sherman and Jördens' work[2], about
one fifth of that should be possible.

BTW: you want to keep even harmonics as low as possible, as these lead
to increase of 1/f noise in the system (see [3] for an explanation)

			Attila Kinali

[1] "Development of a High Precision Multi-Channel Time-to-Digital Converter",
by Nicolas Bucquey, 2016
https://www.ohwr.org/project/r19-tdc-del-a/uploads/a6a30e7969dd05bda87ee27a3112adb9/document.pdf

[2] "Oscillator metrology with software defined radio", 
by Sherman and Jördens,2016
http://dx.doi.org/10.1063/1.4950898

[3] "A Physical Sine-to-Square Converter Noise Model", Attila Kinali, 2018
http://people.mpi-inf.mpg.de/~adogan/pubs/IFCS2018_comparator_noise.pdf

-- 
It is upon moral qualities that a society is ultimately founded. All 
the prosperity and technological sophistication in the world is of no 
use without that foundation.
                 -- Miss Matheson, The Diamond Age, Neal Stephenson