[time-nuts] A simple sampling DMTD

[Jan-Derk Bakker]

Dear Attila,

Thank you for your feedback, replies inline:

On Tue, Oct 15, 2019 at 6:01 PM Attila Kinali <attila at kinali.ch> wrote:
[snip]

> The biggest change I would make, would be to use a higher sampling
> frequency and use an FPGA with a CORDIC as phase detector. Especially
> as your goal is to measure the phase difference of a distribution system,
> where the frequency of both inputs is exactly the same.
>

That's the next step (after I've taken this 8-bit processor as far as it
can go). I'm working on a daughterboard with dual Lattice iCE40 UltraPlus
FPGAs, picked mainly because an open toolchain is available, but also for
their price and QFN48 package options (which I've not found in any other
FPGA family of similar density).

(note that for my purposes I do need to DMTD different frequencies, in
particular the 10MHz system master clock vs the slaved 50MHz clocks on the
individual SDR boards in the phased array).


> The reason for this is rather simple. You are using a LMS fit over
> 32 samples around the zero crossing of a 10Hz signal with a ~10MHz
> sampling clock. This means you have just a few samples over what would
> be otherwise possible.
>

It's not quite that bad, as the double CIC decimator already performs quite
a bit of averaging/filtering. The LMS fit is over 32 samples out of 200 per
period (after the CIC). I expect the largest improvement to come from the
increase in input sample rate.


> The other advantage is, that you operate close to the 1/f corner frequency,
> Ie the effect of 1/f noise hits you (almost) fully. Sampling the full
> sine wave instead gives you the ability to work far away from the 1/f
> corner and thus greatly reduces the effect of 1/f noise.
>

This is definitely true, and at the moment my largest source of errors. As
an intermediate step I'm considering shifting the beat frequency up some
(say to 40...50Hz) and then I/Q demodulating in software.I expect this will
make the filtering of LF noise easier.

If you are interested, I have a parametrizable CORDIC core written
> in VHDL ready for use.


Thank you' I may take you up on that. So far I've been looking at the
(Verilog) CORDIC code in the Ettus USRP sources.

[snip]

> I've been running some tests with a 10MHz sine wave from an Abracon AOCJY1
> > OCXO into a resistive divider, feeding both channels of the DMTD through
> > identical SMA cables (Amphenol 135101-07-M0.50). At the ADC input this
> > yields a -12dBFS sine wave (PSD of the beat note:
> >
> http://www.lartmaker.nl/time-nuts/PSD%20of%20AOCJY1%20into%20the%20LTC2140.pdf
> > ). Over a 34000s measurement period the ZCD as described upthread (least
> > squares fitting of the 32 samples nearest the zero crossing of the rising
> > flank, but without DC/drift correction) shows a time difference of 6.3ps
> > between the two channels, with a standard deviation of 1.6ps (full plot:
> >
> http://www.lartmaker.nl/time-nuts/DMTD%20Time%20between%20zero%20crossings%20with%20resistive%20divider%20(no%20offset%20correction).pdf
> > ).
>
> I am a bit astonished by the high noise level you have. I would have
> expected
> this to yield something below 1ps, judging from what we got from what
> Nicolas
> acheived in his work on the sine exitation based TIC[1].


This is actually better than I had expected, given the drift/LF noise I get
from the LTC2140 ( http://www.lartmaker.nl/time-nuts/LTC2140-14%20drift.pdf
). As I've mentioned upthread I'm looking for a robust way to cancel this
drift; my best plan so far is to calculate the signal average between
subsequent _falling_ edges, and to use this to get the zero level for the
rising edge. (This is a problem which I would expect to have a closed form
solution, even when the period of the sine is not an integer multiple of
the sampling rate. Alas, my undergrad-level math seems to be failing me, so
I'm resorting to the blunt instrument of numerical approximations. I hope
to have more time for this in a week or two; in the meantime I'm very open
for hints.)


> BTW: you want to keep even harmonics as low as possible, as these lead
> to increase of 1/f noise in the system (see [3] for an explanation)
>

Thanks, that's good to keep in mind. What I've shown is the unfiltered
output of the OCXO under test; I've not attempted to do any analog
filtering on this.

Sincerely,

JDB.