[time-nuts] IFCS 2020 tutorial - low noise electronics for time/frequency metrology

[Magnus Danielson]

Hi Attila,

On 2020-07-08 04:25, Attila Kinali wrote:
> Moin,
>
> As some of you know, I have been allowed to give a tutorial on low noise electronics
> for this year's IFCS. As the whole conference has been turned into a virtual one,
> we were asked to record our tutorials and upload them. Additonally to the conference
> I decided to put my tutorial online for everyone to watch. You can find it at
> http://time.kinali.ch/ifcs_2020_tutorial/
> Though, I have to honestly admit, I am not proud of it. There is too much that
> I couldn't fit what should be in there, in in the 75' we were given. And there is
> quite a few things that I think I made too confusing. Nevertheless I hope it can
> be of use for some. Please let me know what you think, especially if you have ideas
> how I could improve the tutorial for the next time I'm giving it.

Not to crack down hard, on it, but a few notes:

1/f is flicker noise, but 1/f^2 and 1/f^3 is not flicker phase noise,
but they do not show up at DC. I assume it is a simplification you made.

In capacitors, two things make them microphonic, voltage over the
capacitor and the high-dielectric constant as this makes it more
sensitive to mechanical stress, and this also tends to make them very
sentistive to thermal stress. So X7R is terrible for instance.

A comment on digital processing which you almost touch on, or rather you
touched on it but I want to extend it some. With low dynamic range
systems (analog and digital), quite a bit of effort has to go into set
gain so that you use most of that dynamic range. In the digital domain,
since bits is becoming cheaper and cheaper, throwing bits onto the
problem can significantly reduce the effort of normalization of level,
since you can let more bits be available before need to round-off and a
bunch of bits before you hit/wrap the rough. This overdimensioning
actually makes the design much more straight-forward. I've done this
myself and with only a few things to care about, I could focus my entire
effort on other pressing design efforts than fine-tuning gain structures.

For 2nd overtone and in fact even overtone supression, beyond reducing
the amplifiers contribution, the PWM of the signal is important.
However, it is relatively easy to feedback PWM error to self-bias the
linear input side to achieve 2nd overtone supression from the PWM
factor. Inbalance in the stages will be fine-tuned by this too. However,
the problem with doing such compensation is that the time-constant of
the feedback integrator needs to be lower than the lowest frequency. For
higher frequency a passive RC scheme can be trivially devised, but for
1-10 Hz beat note regime, active op-amp is needed. It does not remove
the per-stage balancing, but can relax the need to fine-tune it. A
benefit of the low feedback bandwidth is that it's noise contribution
can be kept low and also that it does not have feedback delay issues as
direct signal feedback supression of distorsion.

Another part that you missed (I think) is that classical DMTD setups
have a draw-back, in that the transfer oscillator used to mix-down will
not be seen exactly the same, as the through zero transitions occurs at
different times, so different integration of the noise is done, so the
noise of the transfer oscillator does not cancel as well. Higher beat
notes makes such problems be contained into higher frequency region and
mismatch reduces just by the length of the beat note period, but the
perfect solution is to ADC at the same time and then the decimation and
CORDIC does not care about through-zero time, it will instead look at
the difference in phase for the same time and the noise cancels out
there and only later would a through zero detection occurs, but with
transfer noise issues already pretty good in cancellation. So there is
an additional benefit. The mix-down stage is still relevant for
comparing higher frequency sources, but quite high frequencies can be
treated as "base band" using modern ADCs and FPGA front-end to do
front-end decimation.

So, these notes is really just a few comments or thoughts.

Cheers,
Magnus