[time-nuts] Frequency division by 81

[ew]

On the 15 MHz FE 405 we use an XOR and two Flip Flops  to divide by 3 with a symmetrical output. Four of these will give you symmetry and divide by 81
Bert Kehren

In a message dated 6/19/2020 8:14:31 PM Eastern Standard Time, kb8tq at n1k.org writes:

Hi

The biggest issue is that there are so many variables. They never seem
to get nailed down. What you are seeing is the answer to 20 or more 
“niche” requirements.

For instance:

Is the “phase noise” requirement close in or broadband? ECL is in general 
horrible for broadband phase noise. 

Is the source at UHF or below 10 MHz? A CMOS solution isn’t going to make
much sense at 500 MHz. 

Is a square wave ( to drive logic ) part of the system requirement? Since 
in some cases these are corporate sponsored designs (as opposed to
basement projects) even getting into something that simple is “revealing 
too much of our IP”. 

If the destination is an FPGA, they generally have horrible noise performance. 
That’s true both close in and broadband. What’s “good” there is likely pretty
awful in another context. 

What *is* “good phase noise? To one person, it’s -150 dbc/Hz at 100 KHz offset
on a 10 MHZ source. To the next person it’s 40 db better than that.

As long as none of the details are available, the answers are going to be
very difficult to parse. It’s also why people who do this sort of thing spend 
years learning how to do it. 

Bob



> On Jun 19, 2020, at 7:23 PM, Mark Haun <mark at hau.nz> wrote:
> 
> On Fri, 19 Jun 2020 14:49:01 +0000
> "Poul-Henning Kamp" <phk at phk.freebsd.dk> wrote:
>> Gilles Clement writes:
>>> Could you point me to a practical design example of a Pi divider ?  
>> 
>> Look at Fig 2 in Enrico's paper:
>> 
>>> http://rubiola.org/pdf-articles/conference/2013-ifcs-Frequency-dividers.pdf
> 
> I saw this a while ago and found it interesting, but not being a proper
> time nut myself, I am wondering: are the advantages of this divider
> architecture maintained if you need a square wave output?  Wouldn't the
> triangle->square conversion introduce its own noise, possibly swamping
> the gains of the lambda divider?
> 
> As an aside, I have noticed that every time this question comes up,
> there are a variety of answers, ranging from "use a PICDIV" to "use this
> fancy low-noise architecture" to "use ECL / HC / modern fast logic
> gates."  I read through the replies but never seem to leave the
> discussion knowing any more than I did at its start.  It would be great
> if someone could provide the context to understand the relative merits
> of each suggestion---how they are likely to stack up against one
> another and how you would choose one over the others.  I.e. please
> spend more time explaining why you are right and everyone else is wrong
> ;)  Otherwise, it's just chaff.
> 
> Mark
> 
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