[time-nuts] Assistance needed to understand some V_OCXO stability concepts.

[Jim Harman]

Joe,

I feel your pain. I have only recently obtained a Rb standard, after
several years of experimenting with GPSDOs.

Here are some self-test indications that your system is working correctly
given that you do not have access to fancy test equipment:

-- Put it in "Hold" mode, i.e. with the loop open and the DAC at a set
value. Observe the slope of the phase detector output over time. The slope
corresponds to the measured frequency difference between your oscillator
and the PPS pulses. 1 nsec/sec of slope corresponds to 1e-9 frequency
offset. The slope should be reasonably constant, without a lot of noise.

-- Change the DAC value and observe the change in slope of the phase
detector output. It should match the KV of your oscillator.

-- Close the loop with a time constant of 100 sec or so. After several
hundred seconds, the DAC voltage should be close to constant. Change the
setpoint, i.e.the nominal phase detector value. You should see a hump in
the DAC value as it changes the frequency to eliminate the phase error.
The measured phase should move towards the new setpoint. It may overshoot a
little, but it should not ring and it should settle to the new setpoint.
When the phase error has been eliminated, the DAC should return close to
its previous value, again without a lot of ringing.

Again, this does not measure precisely how well your system is performing,
but it will give a good indication that your loop is locked and stable.

I can send some sample plots of my system if it would help to clarify.


-- 

--Jim Harman