[time-nuts] Assistance needed to understand some V_OCXO stability concepts.

[Joe & Gisela Noci]

Jim,
some further info -
The OCXO I use -  HP_00105-6013 - does not have a lot of info available - I
have searched all over! I have found no definitive info on its KV, etc, so
had to determine it myself.

This I did as follows ( the complexity of my process was to try 'really'
know if it is correct, and if the OCXO behaves according to the correct
Physics!)

The two jpegs,
*KV determination @5V and 6V.jpg* and *KV determination @9V and 10V.jpg*
show the phase detector wrap around during HOLD mode, with the DAC output
set to specific voltages.

For these tests the OCXO was left running for 24hours to warm up and
stabilize as best it could.

The 9V_10V and 5V_6V tests differ in the following:

*     For the 9V_10V test:*

The -EFC Voltage was set to -10V
The +EFC DAC voltage was first set to 8V and the phase detector monitored
on a 'scope. The coarse adjust trim cap in the OCXO was then adjusted so
that the phase detector voltage was close to 1volt and 'not' drifting. This
was monitored and adjusted over a 3 hour period to verify reasonable
stability.

Then the detector voltage was recorded with DAC set to 9V.
Then the DAC voltage was set to +10V and the detector voltage recorded
again.
The phase detector wrap around time were 620sec @ 9V and 300sec @ 10V

I believe this equates to -
 @9V t=620sec so 10/620 = 0.0162Hz
 @10V t=300sec so 10/300 = 0.0333Hz
   *So KV = 0.0333-0.01612 = 0.017 Hz/V*

*        For the 5V_6V Test:*

The -EFC voltage was set to -7V.
With the DAC voltage @+4V first, the OCXO coarse adjust was set so the
phase detector voltage was stable.
Then the DAC was set to +5V, which gave a wrap-around time of t= 550sec
Then with the DAC V= +6V, t=200sec.
*This gives a KV of 0.032 Hz/V*

This all makes sense since the varicap is operating on a different part
capacitance curve slope - at the lower voltages the capacitance is greater,
so the delta_V effect will be greater.

This verifies that the KV values are valid and sensible.

I made use of the 0.033Hz/V settings, as that is what my loop gains are
calculated for.

On Thu, Oct 1, 2020 at 11:12 PM Jim Harman <j99harman at gmail.com> wrote:

> Joe,
>
> I feel your pain. I have only recently obtained a Rb standard, after
> several years of experimenting with GPSDOs.
>
> Here are some self-test indications that your system is working correctly
> given that you do not have access to fancy test equipment:
>
> -- Put it in "Hold" mode, i.e. with the loop open and the DAC at a set
> value. Observe the slope of the phase detector output over time. The slope
> corresponds to the measured frequency difference between your oscillator
> and the PPS pulses. 1 nsec/sec of slope corresponds to 1e-9 frequency
> offset. The slope should be reasonably constant, without a lot of noise.
>
> -- Change the DAC value and observe the change in slope of the phase
> detector output. It should match the KV of your oscillator.
>
> -- Close the loop with a time constant of 100 sec or so. After several
> hundred seconds, the DAC voltage should be close to constant. Change the
> setpoint, i.e.the nominal phase detector value. You should see a hump in
> the DAC value as it changes the frequency to eliminate the phase error.
> The measured phase should move towards the new setpoint. It may overshoot a
> little, but it should not ring and it should settle to the new setpoint.
> When the phase error has been eliminated, the DAC should return close to
> its previous value, again without a lot of ringing.
>
> Again, this does not measure precisely how well your system is performing,
> but it will give a good indication that your loop is locked and stable.
>
> I can send some sample plots of my system if it would help to clarify.
>
>
> --
>
> --Jim Harman
> _______________________________________________
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