[time-nuts] Need help phase locking with small offset

[ed breya]

I totally agree with the others warning to avoid processing too many 
different signals within a FPGA or any kind of part with multiple 
functions. There will always be some amount of crosstalk, so any device 
should be used only for one frequency chain, and only that frequency's 
related harmonics and subharmonics will be in there. It's tempting to 
get as much function as possible in the minimum parts count, but it's 
cleaner to keep things separated - part-wise, and also physically and 
power-wise too, and sometimes separately contained and shielded if needed.

Regarding PLL methods, I'd suggest looking at under-sampling the 
100.0001 MHz with the 10 MHz reference, say, with a DFF, to get the 
direct difference between 10x10 MHz and the 100 MHz + 100 Hz. This would 
skip most of the dividing and give 100 Hz comparison frequency, which is 
nicer than 10 Hz. The 100 Hz reference can easily be made with decade 
dividing from the 10 MHz.

So, instead of lots of dividers, your FPGA or whatever DFFs could be 
used for sampling and metastability correction. In this case, one part 
would hold the sampler processing to make 100 Hz from the two inputs. 
The reference divider should probably be within a separate part, 
according to the concepts of the first paragraph above, keeping its 
intermediate divider frequencies away from the front-end process. Later, 
you can try to do it all in one part and see how it works out.

This all is of course not as frequency-agile as other methods that can 
be done with programmable dividing, but for one or a few fixed offsets, 
may be the simplest approach.

Ed