[time-nuts] Re: RCB-F9T Adapter PCB with USB and 50 Ohm Timepulse SMA Connectors

[Bob kb8tq]

Hi

> On Aug 24, 2022, at 8:51 AM, Carsten Andrich via time-nuts <time-nuts at lists.febo.com> wrote:
> 
> Hi Bruce,
> 
> On 24.08.22 10:26, Bruce Griffiths via time-nuts wrote:
>> I don't see any explicit jitter specs on the BUF602 datasheet either.
>> Have you measured it?
>> How consistent is it from part to part?
> 
> Jitter isn't typically specified for analog amplifiers. At least the ones I worked with never specified jitter. I'm not an expert on analog RF components, but – like I wrote before – I'd assume that the opamp's internal noise to be the only relevant source of additive jitter. Please let me know if that assumption is wrong.
> 
> So far, I haven't measured anything. I've relied on the datasheet values and the BUF602 seems to be the most promising (hand solderable) solution for the job.
> 
> 
>> The jitter of most CMOS families has been measured.
>> For example 74HC buffers typically have ~4ps jitter at room temperature.
> 
> Could you kindly point me to such measurements? I'm curious.
> 
> 
>> Even this is much lower than the jitter of typical FPGAs when the effect of cross coupling from other clock domains such as internal oscillators etc are taken into account.
>> Faster logic families such as 74AC buffers (~ 1ps) have even lower jitter.
>> CMOS devices have a typical propagation delay tempco of around 0.4% of the delay per/C. FPGA gates have similar delay tempcos.
>> Neither the delay tempco nor the jitter is typically specified on CMOS device datasheets nor are they on the BUF602 datasheet so you have to measure them or leverage the results obtained by others.
> 
> These numbers (1~4 ps) are excellent in comparison to the ZED-F9T's timepulse jitter. I estimate about 100 ps jitter

The many ADEV plots posted on the list for the F9x series of parts put the 1 second
ADEV in the 100 to 200 ps range. 

> when integrating John Ackermann's phase noise measurement [1] from 1 Hz to 100 kHz. However, my use case is not limited to the RCB-F9T adapter. I'm looking for a generic solution that will also perform well with low noise OCXOs.

Given the dirt cheap nature of PCB’s these days, the idea making one application 
more expensive / complex is generally not a great approach. Let JLPCB do up 
enough of this or that and do a second board for a different application. Layout
wise, modern tools get things done very quickly.

> 
> I'm taking a decent 100 MHz OCXO with the following phase noise as an example: -100 dBc/Hz @ 10 Hz, -130 dBc/Hz @ 100 Hz, -160 dBc/Hz @ 1 kHz, -170 dBc/Hz @ 10 kHz, 175 dBc/Hz @ >100 kHz.
> That integrates to 18 fs from 12 kHz to 20 MHz (range is used for all subsequent jitter values). The LMK1C110x weighs in at 8 fs typ. (20 fs max.) for f = 156.25 MHz [2] and the LTC6957-3 has 90 fs typ. for f = 100 MHz [3].
> 
> The BUF602's input voltage noise of 4.8 nV/√Hz equals -153 dBm/Hz into 50 Ohm. Better, non hand solderable opamps exists, e.g., BUF802 with 2.3 nV/√Hz (-160 dBm/Hz) and AD8000 with 1.6 nV/√Hz (-163 dBm/Hz). Depending on the OCXO's output level, the opamps' additive noise is barely measurable over the OCXO's phase noise. Assuming +7 dBm OCXO output, the AD8000 has a -170 dBc/Hz noise floor. Hence, I'd expect negligible additive jitter.

But your -175 dbc phase noise is long gone …. 

A discrete buffer typically is the right answer in most cases for low phase noise. 

Bob

> 
> With 1~4 ps jitter, the logic buffers are significantly worse. Also in terms of temperature coefficient, the opamps are better off, because their overall propagation delay is smaller. The BUF602 datasheet reports 300~600 ps group delay [4, Fig. 12].
> 
> Best regards,
> Carsten
> 
> [1] https://hamsci.org/sites/default/files/publications/2020_TAPR_DCC/N8UR_GPS_Evaluation_August2020.pdf#page=29
> [2] https://www.ti.com/lit/ds/symlink/lmk1c1103.pdf#page=6
> [3] https://www.analog.com/media/en/technical-documentation/data-sheets/6957fb.pdf#page=9
> [4] https://www.ti.com/lit/ds/symlink/buf602.pdf#page=9
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