[time-nuts] Re: RCB-F9T Adapter PCB with USB and 50 Ohm Timepulse SMA Connectors

[Carsten Andrich]

Hi Bob,

On 26.08.22 17:53, Bob kb8tq wrote:
> Hi
>
>> On Aug 26, 2022, at 1:08 AM, Carsten Andrich 
>> <carsten.andrich at tu-ilmenau.de> wrote:
>>
>> Hi Bob,
>>
>> On 24.08.22 21:20, Bob kb8tq wrote:
>>>> [...] However, my use case is not limited to the RCB-F9T adapter. I'm looking for a generic solution that will also perform well with low noise OCXOs.
>>> Given the dirt cheap nature of PCB’s these days, the idea making one application
>>> more expensive / complex is generally not a great approach. Let JLPCB do up
>>> enough of this or that and do a second board for a different application. Layout
>>> wise, modern tools get things done very quickly.
>>
>> You're right in terms of component and (automated) production cost, 
>> but I'm also looking at it from an engineering cost perspective. 
>> Qualifying multiple different solutions for a similar* problem is 
>> costly. Hand-soldering the SMA connectors is already more expensive 
>> than the price difference between logic buffers and buffer opamps. 
>> Add the connectors on top and I'd doubt total savings on components 
>> would ever amortize the added engineering costs for producing a few 
>> dozen devices.
>>
>> *) By similar problem I mean low-noise buffering of arbitrary 
>> wideband signals with 50 Ohm source impedance into both high 
>> impedance and 50 Ohm loads. By arbitrary wideband signal I refer to 
>> any kind of typical timing signal, whether it's a pulse (not 
>> necessarily only 1PPS) or periodic rectangle at frequencies up to a 
>> few hundred MHz.
>>
>
> If this is a commercial product that is targeted at a market then yes, 
> the qualification
> process gets into it. For a hobby use sort of design, it’s a pretty 
> quick process and
> “part of the fun”. If this is indeed a commercial design?

It's a personal hobby project to deepen my circuit design experience and 
to develop a proof-of-concept GNSSDO. However, I have a clear goal: A 
100 MHz low phase noise mobile GNSSDO [1]. Nothing commercially 
available satisfies my requirements.

Hence, the way is not the goal. For sth. as circumstantial as a low 
noise 50 Ohm line driver, I don't want to spend time on experimenting 
with and comparing different options (maybe "qualifying" was the wrong 
term). For now, I prefer a straightforward one-fits-all solution with 
decent performance (i.e., opamp like BUF602). If further down the road 
that turns out to be insufficient, I can still delve into sth. discrete 
like you suggested below.


>>>> I'm taking a decent 100 MHz OCXO with the following phase noise as an example: -100 dBc/Hz @ 10 Hz, -130 dBc/Hz @ 100 Hz, -160 dBc/Hz @ 1 kHz, -170 dBc/Hz @ 10 kHz, 175 dBc/Hz @ >100 kHz.
>>>> That integrates to 18 fs from 12 kHz to 20 MHz (range is used for all subsequent jitter values). The LMK1C110x weighs in at 8 fs typ. (20 fs max.) for f = 156.25 MHz [2] and the LTC6957-3 has 90 fs typ. for f = 100 MHz [3].
>>>>
>>>> The BUF602's input voltage noise of 4.8 nV/√Hz equals -153 dBm/Hz into 50 Ohm. Better, non hand solderable opamps exists, e.g., BUF802 with 2.3 nV/√Hz (-160 dBm/Hz) and AD8000 with 1.6 nV/√Hz (-163 dBm/Hz). Depending on the OCXO's output level, the opamps' additive noise is barely measurable over the OCXO's phase noise. Assuming +7 dBm OCXO output, the AD8000 has a -170 dBc/Hz noise floor. Hence, I'd expect negligible additive jitter.
>>> But your -175 dbc phase noise is long gone ….
>>
>> Unfortunately, yes. If phase noise is of most concern, then RF gain 
>> blocks are obviously a better choice than buffer opamps. The HMC589 
>> has 4 dB noise figure down to DC (allegedly) and even comes with 
>> phase noise specs [1]. However, I doubt these gain blocks are a 
>> suitable choice if 3.3V CMOS logic levels are required.
>>
>> Regardless, the LTC6957-3 I plan on using to convert a 100 MHz sine 
>> to 3.3V CMOS is considerably worse than the suggested buffer opamps 
>> in terms of phase noise. Gotta spin off another thread on that ...
>>
>>
>>> A discrete buffer typically is the right answer in most cases for low phase noise.
>>
>> Are you referring to the same logic buffers that have 1~4 ps jitter? 
>> How are these better than dedicated clock ICs with < 90 fs jitter 
>> specs and a noise floor above my suggested opamps?
>>
>
> No, an amplifier made up of discrete transistors, resistors, 
> capacitors and
> the like.

Sorry, got it now.


>
>> As always, I'd be grateful for references to exemplary components, 
>> datasheets, designs, and measurement results.
>>
> Unfortunately that measurement data and the documentation that ran up 
> to it is
> property of my various employers over the last 50 years of designing 
> OCXO’s and
> GPSDO’s.

Alright, thanks for sharing your experience.

Best regards,
Carsten


[1] 
https://febo.com/pipermail/time-nuts_lists.febo.com/2022-April/105583.html