[time-nuts] Re: 10 MHz TCXO periodically jumping 20 mHz up and down, cause identified

[Magnus Danielson]

Erik,

So, your pick of VC-TCXO is one that obviously seems to use the 
fractional synthesis to both set the output frequency as well as 
compensate for temperature. The modulations you have will be intrinsic 
to the pick.

As you lock your VC-TCXO to a GPS, the average frequency will be locked 
to the GPS, but the variations you have from steering will remain. The 
control theory of a PLL lock says that you will low-pass filter the 
signal on the reference and high-pass filter the noise of the 
oscillator. The cut-over frequency is the same, the bandwidth of the 
PLL. The actual responses will also be coloured by the damping factor, 
which should be kept high to avoid bumps. A rule of thumb is to ensure 
you keep the damping factor at least 3 or higher. Now, that remains of 
you shifts will be the spikes of the shift, and you really do not get 
rid of them unless you have a second cleanup PLL that can low-pass 
filter out them. This assumes naturally that you have a quiet oscillator 
in the clean-up, and the lesson being, you should be using that 
oscillator instead most of the times. The special case is when you have 
a somewhat dirty but stable oscillator so you can do hold-over in 
unlocked conditions, and then use a clean but less table oscillator as 
clean-up. However, many times you can just get a clean oscillator and 
avoid the issue, resulting in a simpler and cleaner design, which may be 
beneficial as you get a more compact and less power-hungry setup.

These disturbances can eat your precision if you do frequency counters 
or spectrum analysis. Actual frequency precision is not the only 
measure, but phase-noise and ADEV stability (as perscribed in IEEE Std 
1139).

It sounds like you have yourself a fine little oscillator there, but it 
may be unfit for your application. I've seen that so many times. Being 
"in spec" in terms of the datasheet does not necessarily makes it "in 
spec" for the application. At best datasheets help you coarse-select 
candidates, but then they need to be tested that their basic behaviour 
is compliant with all the performance needs of the actual application. 
Learning what is relevant and not for an application is a learning 
experience, and one set of experience may or may not be relevant for 
another users needs. If one only use high quality oscillators, the types 
of tricks being used in high volume low cost oscillators to provide some 
set of performance can cause surprises. Either one learn to live with 
them, or find ways to compensate them.

For instance, the low frequency PWM pattern you have on frequency you 
measured creates a phase-deviation that looks like a triangular wave 
shape. It will sweep from equal-slope triangular over to sawtooth shape. 
The acceleration spikes as frequency shift at th ends will stress a 
follow-up loop. The time-deviation of the oscillator will limit what you 
can do with it for other measures. The time-deviation can be 
characterized in the standard MTIE curve that measure max max-to-min 
time-deviation. This is important in telecom applications, as it 
translates to buffer-size. It will also be important in time-interval 
measurements.

OK, do let's calculate the peak-to-peak of the phase. You measured a 
step difference of about 20 mHz and a period of 107 s. Now let's just 
assume that we set it up to synthesize 10 mHz, that is just inbetween 
the two steps. This means half the time it would be set to the lower 
frequency and the other half to the high frequency, and it now becomes 
trivial to see that the frequency synthesis goal is reached. However, it 
means that it spends about 50 s at +10 mHz and then 50 s at -10 mHz of 
that average. This produces a phase-ramp going -0.5 s and then +0.5 s, 
since 0.01 * 50 = 0.5 s. The peak-to-peak time is thus half a second. 
That is really bad. This is the problem with long PWM on frequency.

For one design I did, I built a reversed PWM spectrum modulation, which 
actually had about the same logic complexity of PWM. It forced the most 
significant energy to the highest possible frequency, where it becomes 
trivial to filter. For that system I had both an analog filter and the 
filtering of the VC-OCXO. The side-consequence is also that the ramp of 
phase error keeps being moved up and down at high rate and only ower 
components would be seen, but much damped. Any remaining phase issue is 
then controlled by the loop as it is a phase-lock and those errors is at 
low enough frequency to be suprpessed by the high-pass function of the 
PLL. Also, for my case, the issue was small since it was a way to cram 
out 19 bits out of a 16 bit DAC, so the amplitude was scalled down by 
1/65536 of full-scale and then by the sensitivity of the EFC input.

We have to do these ugly tricks in real life engineering, but the trick 
is learning to cheat where it doesn't hurt too much. Telling about these 
things I hope is illustrative enough to be a good reading.

Cheers,
Magnus

On 2022-02-19 09:24, Erik Kaashoek wrote:
> Thanks for all the excellent info
> The TCXO is actually a VC-TCXO at 10MHz intended for use in a cheap 
> GPSDO where the ambition is to have 1e-9 frequency accuracy so the 
> 2e-9 jump was just too high.
> The VC-TCXO had its own low noise voltage regulator but the Vtune was 
> connected to a variable voltage divider between GND and the Vcc of the 
> VC-TCXOÂ  through a low pass filter so even with its own voltage 
> regulator any change in current in the TCXO can change the supply 
> voltage and feedback through the variable voltage divider.
> It was expected that only slow changes in current could happen because 
> of temperature changes as the temperature control is very fast, loop 
> bandwidth well within one second, and these where filtered out  by a 
> low pass filter after the variable voltage divider.
> To test if the jump up and down was caused by a current to Vtune 
> feedback the Vtune was set to Vcc, 1/2 Vcc, 1/4 Vcc and GND.
> The result was interesting:
> Vtune | Max jump
> Vcc    | 6e-9
> 1/2 Vcc | 3e-9
> 1/4 Vcc | 1.5e-9
> GND | no jump
> This suggests the jump is indeed caused by feedback from the current 
> changes through the variable voltage divider into Vtune and there is a 
> digital circuit inside the VC-TCXO with changing current consumption 
> causing the 107.34 seconds periodicity.
> To confirm the feedback was indeed the cause the variable voltage 
> divider was connected to a 3.7 V battery instead of Vcc and indeed, no 
> more frequency jumps!
> The ADEV of this cheap VC-TCXO with Vtune at 1/2 Vcc is not bad:
> 0.1 s | 2e-10
> 1 s | 1.5e-10
> 10 s | 0.9e-10
> 100 s | 2e-10
> With the Vtune at GND the ADEV is even much better so there is still 
> some more investigating to do.
> Some DAC's with internal voltage references have been ordered to test 
> if it  is possible to connect the DAC to the same Vcc (to save cost) 
> and still have a stable but variable Vtune without feedback .
> If this does not work the DAC will need its own voltage regulator.
> Again thanks to all the people that replied, I'm learning a lot.
> Erik.
>
>
>
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