[time-nuts] Re: DIY Low offset Phase Noise Analyzer (Erik Kaashoek)

[Magnus Danielson]

Hi,

On 2022-07-05 12:13, Mike Monett via time-nuts wrote:
> You stated:
>
> Mike,
> The phase detector is an ADE-1 mixer, the IF output of the mixer goes
> into a loop filter that has a corner frequency of about 0.2Hz to enable
> Phase noise measurements down to 1Hz offset
>
> That is your problem. A double balanced mixer is an exclusive-or phase
> detector. The lock range is determined by the loop bandwidth, as you have
> found.
>
> The phase-frequency detector is completely different. It will lock to any
> signal in the lock range, independent of loop bandwidth. You can have a
> bandwidth of 0.001 Hz, and it will still lock. Think of what this could do
> for your phase measurements.

Actually, there is two schools here.

There is the school of stateless phase-detectors (such as mixers) and 
the school of stateful phase-detectors (such as three-state mixers).

Now, in the school of stateless phase-detectors, mixers, XOR-gates, 
samplers etc. the capture range becomes dependent on the loop gain.

For passive lag filters, you will need a significant static 
phase-difference on the input to provide the state of the EFC to 
compensate on the frequency. It's very simply that the DC volt 
difference coming out of the detectors, through the DC gain of the 
filter is then what becomes the EFC.

In active lag filters, you add additional gain, and this requires lower 
phase detector voltage to support the same EFC error.

Both these actually have an implicit state in the phase detector to 
compensate the lack of state elsewhere. It is just not that the phase 
detector holds explicit state.

In PI filters, the state of the frequency error is moved from the phase 
detector to the filter. The integrator has close to infinity in DC gain 
(naturally limited in practice, but for many purposes we can assume it 
being infinite) such that it drives the DC phase offset out of the phase 
detector to zero and builds up the needed EFC state in the integrator 
capacitor. This have the benefit that capture range is in theory 
unlimited, but even if the actual range is in practice limited, it is so 
wide that we can treat it as infinite for most cases. The PI loop those 
do not need any form of aiding to lock up. However, aiding it can 
increase lock-up time. You could either pre-trim the EFC or you could 
increase the PLL bandwidth to achieve quick lockup. The later is 
actually very simple and has very huge impact.

The thing people do wrong with PI filters is to scale the bandwidth on 
the output side of the integrator. This is wrong, as one then needs to 
scale the output to maintain the acquired state to match the needed EFC. 
The right way to do it is to scale it on the input side. That way the 
scaling to EFC is maintained and no state-scaling is needed.

As one scales the bandwidth through I one needs to scale P accordingly 
to maintain good damping properties.

Fairly simple PI-loop setups allow for good lockup and stability properties.

Cheers,
Magnus