[time-nuts] Re: Seeking feedback on a HW Architecture for a DIY two channel timer/counter and frequency reference

[Carsten Andrich]

Hi Erik,

very interesting project. I've been using software-defined radios for 
5~6 years now to evaluate our various frequency references (mostly 
GNSSDOs) [1]. However, the resulting measurement setups are quite 
expensive (>20k€ for 8 synchronous channels with USRPs X310), bulky 
(2HE, 500 mm depth), heavy (>10 kg), and power hungry (>100 W). I've 
been sporadically pondering how to design a cheap and compact, yet 
highly accurate alternative for about a year now. My current, unverified 
idea for a quad channel time interval counter is to combine 4 TDC7200 
with an STM32's 32-bit timer capture (also has 4 channels). The TDC 
should enable ~50 ps resolution.

How do you plan to implement the edge detection (blocks "A/B edge 
detect")? What resolution are you designing/hoping for? What's the 
purpose of the CPLD, i.e., what does it do that the MCU can't?

Best regards,
Carsten

[1] https://arxiv.org/abs/1803.01438

On 16.07.22 16:31, Erik Kaashoek via time-nuts wrote:
> Some time ago I have shared some info on the timer/counter project I'm 
> working on.
> Based on the excellent feedback from this community I've made some 
> changes to the HW architecture.
> The goal is a simple and cheap HW, possibly leading to a product that 
> can be sold for around $100.
> An architecture level overview can be found here: 
> http://athome.kaashoek.com/time-nuts/Architecture_2.JPG
> Not shown is a touch LCD display that runs the user interface.
> The device will have two inputs (channels A and B) with AC or DC 
> coupling, user definable trigger levels and up or down trigger edge.
> One input will have an optional pre-scaler
> A third input can be used either for a GPS antenna for the internal 
> 10MHz GPSDO or for input of an external 10MHz reference.
> A separate output can provide either the internal 10MHz reference or a 
> frequency derived by integer divide from this internal reference, such 
> as 1MHz or 1Hz. The phase of the output is locked by the GPSDO to the 
> GPS PPS
> Given the form factor, 4 inputs/output is the maximum possible.
> Does this setup of inputs/output make sense?
> Are there any suggestions for improving this architecture?
> Erik.
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