[time-nuts] Re: Seeking feedback on a HW Architecture for a DIY two channel timer/counter and frequency reference

[Erik Kaashoek]

Hi Carsten,

On 16-7-2022 21:44, Carsten Andrich via time-nuts wrote:
> My current, unverified idea for a quad channel time interval counter 
> is to combine 4 TDC7200 with an STM32's 32-bit timer capture (also has 
> 4 channels). The TDC should enable ~50 ps resolution
I had a look at the TDC7200 and it could fit in the design but the time 
resolution is unbalanced with the TCXO performance. Yes, for DMTD it 
could be nice but 5ns resolution should be good enough
> .
>
> How do you plan to implement the edge detection (blocks "A/B edge 
> detect")? 
Two fast comparators ( 
https://datasheet.lcsc.com/lcsc/2206101816_Gainsil-GS8743-TR_C840038.pdf 
) and DAC's to set the trigger level
> What resolution are you designing/hoping for? 
5 ns or, if overclocking, 4 ns
> What's the purpose of the CPLD, i.e., what does it do that the MCU can't?
It replaces all the small logic IC's.  An example is the capture logic 
and the edge selection that must be before the capture logic, and it is 
used as an IO extender to drive the switches in the signal path 
(high-Z/50 ohm, pre-scaler, etc...)

A complete prototype using discrete logic instead of the CPLD is working 
up to 100 Mhz and the pre-scaler is proven up to 4 GHz. The SW is fully 
functional, including interpolation for  both frequency and phase, 
although still a bit rough. There is still a certain amount of phase 
pulling due to the non optimal layout.
Erik.