[time-nuts] Re: Seeking feedback on a HW Architecture for a DIY two channel timer/counter and frequency reference

[Carsten Andrich]

Hi Erik,

On 17.07.22 07:28, Erik Kaashoek via time-nuts wrote:
> Hi Carsten,
>
> On 16-7-2022 21:44, Carsten Andrich via time-nuts wrote:
>> My current, unverified idea for a quad channel time interval counter 
>> is to combine 4 TDC7200 with an STM32's 32-bit timer capture (also 
>> has 4 channels). The TDC should enable ~50 ps resolution
> I had a look at the TDC7200 and it could fit in the design but the 
> time resolution is unbalanced with the TCXO performance. Yes, for DMTD 
> it could be nice but 5ns resolution should be good enough

Particularly for measuring short intervals, which is relevant for GNSSDO 
comparison, the TCXO should have negligible effect. Assuming a 2 ppm 
frequency error, a time interval of 25 us corresponds to an error equal 
to the TDC's 50 ps resolution.


>> How do you plan to implement the edge detection (blocks "A/B edge 
>> detect")? 
> Two fast comparators ( 
> https://datasheet.lcsc.com/lcsc/2206101816_Gainsil-GS8743-TR_C840038.pdf 
> ) and DAC's to set the trigger level

Do you expect any propagation delay mismatch between the comparators to 
affect the results?


>> What resolution are you designing/hoping for? 
> 5 ns or, if overclocking, 4 ns 

Some STM32 support timer capture with up to 200~250ish MHz (e.g., 
STM32F745 @ 216 MHz [1] and STM32H742 @ 240 MHz [2]), which would 
natively enable your desired resolution. I've verified using timer 
capture for this purpose works with an STM32G474 at 174 MHz and a ZED-F9T.


Best regards,
Carsten


[1] https://www.st.com/resource/en/datasheet/stm32f745ie.pdf#page=33
[2] https://www.st.com/resource/en/datasheet/stm32h742bg.pdf#page=42