[time-nuts] Re: Seeking feedback on a HW Architecture for a DIY two channel timer/counter and frequency reference

[Carsten Andrich]

Hi Erik,

On 17.07.22 21:40, Erik Kaashoek wrote:
> Carsten
> Everything that is in the MCU block is inside the CPU I'm using.
Sorry, misunderstanding on my side. Somehow assumed your architecture 
included some timing features already inside the CPLD.
> Not only the comparators will influence path delay, also the other 
> differences in the signal path so there is the need for calibrating 
> this out.
Sure. Presumably, the longer the propagation delay of a component, the 
larger its potential time variance, e.g., due to temperature dependence. 
That's why I keep all components that are not explicitly designed for 
timing or clocking (particularly 74s) away from timing-critical signal 
paths. The TDC7200 is temperature compensated via self-calibration [1]. 
Matthias Welwarsky had a ~1ns/K temperature coefficient in his GNSSDO 
design [2], so I wanted to raise awareness for this issue while you're 
still in the design phase. If you're aiming for ~5 ns 
accuracy/resolution, temperature dependence could be negligible, 
considering your comparator's propagation delay.
> I was worried about the limited ADEV of the TCXO would limit 
> credibility of measuring A->B intervals of max 10 seconds with 50 ps 
> resolution.
For such long intervals, the stability of the reference will certainly 
affect the measurement to the extent of the oscillator accuracy. If a 
1~2 ppm error is too much for your use case, that's certainly an issue.

> Erik
Best regards,
Carsten

[1] https://www.ti.com/lit/ds/symlink/tdc7200.pdf#page=9
[2] 
https://www.eevblog.com/forum/projects/diy-gpsdo-project-w-stm32-tdc7200/