[time-nuts] Re: Seeking feedback on a HW Architecture for a DIY two channel timer/counter and frequency reference

[Bob kb8tq]

Hi


> On Jul 18, 2022, at 4:58 AM, Magnus Danielson via time-nuts <time-nuts at lists.febo.com> wrote:
> 
> Hi Erik,
> 
> On 7/16/22 16:31, Erik Kaashoek via time-nuts wrote:
>> Some time ago I have shared some info on the timer/counter project I'm working on.
>> Based on the excellent feedback from this community I've made some changes to the HW architecture.
>> The goal is a simple and cheap HW, possibly leading to a product that can be sold for around $100.
>> An architecture level overview can be found here: http://athome.kaashoek.com/time-nuts/Architecture_2.JPG
>> Not shown is a touch LCD display that runs the user interface.
>> The device will have two inputs (channels A and B) with AC or DC coupling, user definable trigger levels and up or down trigger edge.
>> One input will have an optional pre-scaler
>> A third input can be used either for a GPS antenna for the internal 10MHz GPSDO or for input of an external 10MHz reference.
> This is useful. If you also can make it accept 5 MHz it will be even better. Depending on where you are, 5 or 10 MHz is the base frequency.
>> A separate output can provide either the internal 10MHz reference or a frequency derived by integer divide from this internal reference, such as 1MHz or 1Hz. The phase of the output is locked by the GPSDO to the GPS PPS
>> Given the form factor, 4 inputs/output is the maximum possible.
> 
> Each additional input after 2 will give additional capability to measure things.
> 
>> Does this setup of inputs/output make sense?
>> Are there any suggestions for improving this architecture?
> 
> While not directly visible in the architecture, there is two things I'd like to high-light:
> 
> First is the input side, it needs to have as low noise as possible, but also amplification around the trigger point to increase slew-rate with as little bandwidth as needed. This is the traditional wisdom at least, for best single-shot resolution performance. Then you have people like me that points out more subtle points, but those becomes valid only after:
> 
> The maximum sample rate of the TIC is important. For good result, you want to decimate the samples before or integrated with phase, frequency and linear drift estimation. The gain of that depends heavily on the hardwares ability to do high rate of samples, since this can then increase the amount of samples that goes into each estimation.
> 
> With such decimation in place on high enough sample rate, some noise can actually be beneficial. This will reduce the single-shot resolution for the benefit of decimated resolution. This technique was in commercial use in the 70thies, but before it could be fully analyzed.

Quick one on noise injection and decimation:

Some structures for measuring time have a very abrupt boundary between two readings.
You put in >2 to  <48 ps and you always get a LSB of 0 out. You put in >52 to <98 ps and 
you get a LSB of 1. Move to the previous / next bins and something similar happens. 

If your very stable signal is slowly creeping along over a 40 ps range this is not a great thing. 
The device gives very little useful data for further processing. Yes, you do need a signal that
has << 40 ps of jitter in order to even see this happening ( in the example case ….). In a world
full of ground loops and funky coax this may not be as easy as you might think.

The implication above is that this happens in the middle of the bin. That may not be the case. 
The switch point in adjacent bins may be very different. At some point this can get pretty 
strange. Significantly un-equal bin sizes are tough to deal with. 

This sort of thing is hardly unique to TDC’s. There are a number of processes that do this
sort of thing.

Bob



> 
> Cheers,
> Magnus
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