[time-nuts] Re: Catching range of GPSDO

[Tom Van Baak]

Hi Erik,

1) When your device powers up you wait for GPS acquisition. The wait 
could be seconds, or maybe minutes. It depends on many factors, some of 
which you control -- such as the choice of make / model receiver, 
capacitor / battery backup, saved state in eeprom, a good RTC, etc. Some 
of which you cannot control -- such as what kind of antenna the user 
has, how long and what kind of cable is used, where in the world they 
are located, what kind of reception indoors, what level of interference 
is present, how long since they last powered up your device, etc.

During this waiting time you don't know your TCXO frequency or phase. 
This is normal.

2) When the first 1PPS arrives, you can tell if your TCXO phase is wrong 
to within, say, 25 ns. Part of that error is your GPS receiver, part of 
that error is TCXO noise, part of that error is TIC resolution. This is 
normal.

Set the TCXO/counter phase (aka "jam sync"). Now you've gone from not 
knowing the time or frequency to having your TCXO in phase to within a 
few clock cycles. This gets you 99.99999% of the way there (in phase). 
On the very first 1PPS.

Note that since your device lacks 1PPS output there is no need to 
physically sync TCXO phase or zero a h/w counter. It can all be done 
with a virtual counter inside the MCU.

3) Now wait for the next 1PPS. How much did the phase change? If your 
TCXO is off by 1e-6 you will see 1 us phase change. If it's 1e-7 then 
you will see 100 ns. Your system is able to detect this. Adjust the DAC 
immediately. Now not only is your 1PPS close to correct but your 
frequency is also. This gets you 99.99999% in frequency, already by the 
2nd 1PPS.

If your TCXO is within 1e-8 you may have to wait a few seconds before 
you can reliably detect phase and frequency offsets on the order of 10 
ns and 10 ns/s, respectively.

The key is not to wait some fixed N seconds and make a measurement. 
Instead check the phase and frequency offset every second and let the 
frequency error drive the process, not some fixed gate time.

4) So within a few seconds you can achieve 1e-8 levels of accuracy. 
Similarly, it may take 10 s or 20 s to set the TCXO to 1e-9 levels. At 
this point you can pre-load your parameters, filters, and enable your 
PLL / FLL algorithm for longer-term use.

The dynamics at power up can be completely different than steady-state 
so it's not clear to me that the same locking process should be used for 
both. For instrument-grade GPSDO this doesn't matter that much because 
they tend to be powered up once and then left running for days or years. 
But for a portable, battery, handheld unit frequent power cycling is 
expected and the user would like accurate results within seconds, not 
wait for some PhD level PLL / FLL / Kalman filter to settle to textbook 
perfection.

Note also all of this can be simulated. You have lots of raw data. 
Collect both warm- and cold-start data too. Then simulate power up at 
random points within your data set. See how fast you can get to 1e-9.

5) You DAC sounds insufficient to me. 1e-11 * 32768 = 0.3 ppm. What are 
the drift specs of your TCXO? Do you want all your products in the trash 
after the first year because the DAC runs out of tuning range? Even the 
famous hp 10811 has a drift spec of 5e-10/day and 0.1 ppm/year.

One solution is to provide a screwdriver hole so that the user can make 
a manual EFC adjustment when the DAC gets out of range. This is not 
something you'd do on a professional instrument-grade GPSDO, but it 
might be totally acceptable, even clever, on a low cost handheld unit.

/tvb

On 3/3/2022 12:36 PM, Erik Kaashoek wrote:
> The GPSDO I'm building started with frequency locking but now I'm adding
> phase locking so the time stamping counter can be on GPS time.
> A first version works with a PI controller setting the vc-tcxo Vtune DAC
> based on the phase difference of the 10 MHz with the PPS phase. Due to
> tolerances the tcxo frequency range is big and is set by a 16 bit DAC where
> 1 bit is about 2e-11 frequency change.
> Once the DAC value is close to the correct frequency the loop catches
> nicely but if the setting is far off catching takes a long time.
> A possible solution is to use the frequency error to set the DAC close to
> the optimal frequency for catching.
> Speed of catching is important as the design is intended to only be
> switched on when needed.
> Does anyone have pointers to info on how to do quick catching in such a
> control loop?
> Erik
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