[time-nuts] Re: Optimizing GPSDO for phase stability
Magnus Danielson
magnus at rubidium.se
Sun May 29 16:29:41 UTC 2022
Hi Erik,
On 2022-05-28 10:29, Erik Kaashoek via time-nuts wrote:
> Hi Magnus,
>
> I've insufficient understanding of PLL's to grab the full meaning of
> your remark on "shift of the resonance"
OK, so a PI-controlled PLL has two basic characteristics, it's resonance
frequency and it's damping factor (reciprocal of Q-factor).
You will get a frequency where there is a positive gain, giving
jitter-peaking, as the phase-noise (aka jitter) from the reference port
get's increased gain over to the output. The I factor of the PI-looped
PLL is proportional to the square of this characteristics. The P factor
is then proportional to the resonance frequency times the damping factor.
Now, this peak of noise energy will have a tell-tail in the ADEV plot as
being similar to the wavey pattern you get from a pure sine of the same
frequency as the mid-point of the jitter-peaking. What I was observing
was how that peak moved in the ADEV plot, and suggested that a better
view could be given in the phase-noise domain.
For jitter-peaking, see for instance Wolaver "Phase-locked loop circuit
design".
> Attached are the 3 phase PSD plots from stable32. Is that what you
> where looking for?
> Tick_01 is for Kp=0.1, Tick_004 is for Kp=0.04, etc...
> With Kp=0.01 there seems to be a peak at 3e-3Hz, for the other Kp it
> seems to be less evident if there is a resonance peak in the phase.
> Also attached are the Frequency PSD plots (Freq_001, Freq_004,
> etc...)Â and these show a clear shift of the peak.
Indeed, as I suspected
> Does this shift imply the loop is not yet tuned optimal?
I wonder how your model and parameters work.
I tend to label the phase-detector to EFC gain factor as P and the
phase-detector into the integrator (who's output is added to the EFC)
gain factor as I.
VD = PhaseDetector output
VI = VI + VD*I
VF = VI + VD*P
EFC = VF
I tend to model it as analog continuous time, but similar enough
properties occurs in digital discrete time.
In such a model, the steering parameters is resonance frequence f0 and
damping factor d.
I = KI * f0^2
P = KP * f0 * d
The fixed constants KI and KP can be derived from loop and scaling
parameters.
Notice that there is no single gain-point which will only dial for f0,
but both I and P need appropriate scaling.
To keep jitter peaking reasonable, the damping factor d should be 3 or
higher. However, for test purposes it can be set lower to make jitter
peaking and thus resonance frequency easier to observe.
Cheers,
Magnus
> Erik.
>
>
> On 27-5-2022 21:30, Magnus Danielson via time-nuts wrote:
>> Dear Erik,
>>
>> On 2022-05-27 18:02, Erik Kaashoek via time-nuts wrote:
>>> The GPSDO/Timer/Counter I'm building also is intended to have a
>>> stabilized PPS output (so with GPS jitter removed).
>>> The output PPS is created by multiplying/dividing the 10MHz of a
>>> disciplined TCXO up and down to 1 Hz using a PLL and a divide by
>>> 2e8. No SW or re-timing involved.
>>> The 1 PPS output is phase synchronized with the PPS using a SW
>>> control loop and thus should be a good basis for experiments that
>>> require a time pulse that is stable and GPS time correct.
>>> As I have no clue how to specify or evaluate the performance of such
>>> a PPS output I've done some experiments.
>>> In the first attached graph you can see the ADEV of the GPS PPS (PPS
>>> - Rb) and the 1 PPS output with three different control parameters
>>> (Tick - RB)
>>> As I found it difficult to understand what the ADEV plot in practice
>>> means for the output phase stability I also added the Time Deviation
>>> plot as I'm assuming this gives information on the phase error
>>> versus the time scale of observation.
>>
>> The ADEV plot is the frequency stability plot, so it can be a bit
>> challenging to use it for phase stability.
>>
>> The TDEV plot is the phase stability plot, so it is more useful for
>> that purpose.
>>
>> There is a technical difference between these beyond the difference
>> of frequency vs phase stability, and that is that ADEV is the
>> frequency stability for a Pi-counter where as TDEV is the phase
>> stability for a Lambda-counter, where MDEV is the frequency stability
>> for the Lambda-counter. There is no standardized phase-stability for
>> Pi-counter. For a nit-pick like me it is significant, but for others
>> it may be mearly a little confusing.
>>
>>> Lastly a plot is added showing the Phase Difference. All plots where
>>> created using the linear residue as the Rb used as reference is a
>>> bit out of tune.
>>> Also the TIM files are attached
>>> The "PPS - RB" and "Tick - RB Kp=0.04" where measured simultaneously
>>> and should show the extend to which the GPS PPS is actually drifting
>>> in phase versus the Rb and how this impacts the output phase of the
>>> stabilized output PPS.
>>> My conclusion is that a higher then expected Kp of 0.1 gives the
>>> most stable output phase performance where the best frequency
>>> performance is realized with a Kp = 0.04
>>> I welcome feedback on the interpretation of these measurements and
>>> the application of output phase stabilization.
>>
>> Since Kp is proportional to the damping-factor, this is completely
>> expected result for me. As the damping factor increases, the jitter
>> peaking decreases, and thus the positive gain at the loop resonance
>> frequency.
>>
>> What I seem to notice is that the resonance seems to move with Kp
>> shifts, rather than having a peak of fixed frequency/tau. Doing
>> phase-noise plots of the data in Stable32 should be a way to see if
>> this is an actual shift or just an apparent shift.
>>
>> The details of the PI-loop control may be relevant to correct for if
>> the f_0 shifts as consequence of changing Kp rather than changing Ki.
>>
>> The trouble one faces with a PLL is that optimum phase stability and
>> optimum frequency stability comes at different PLL bandwidth
>> settings. Keeping the damping factor high to keep jitter peaking low
>> is however a common optimization.
>>
>> Cheers,
>> Magnus
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