[time-nuts] Re: What phase variations to expect in a DMTD due to temperature fluctuations?

[Attila Kinali]

Moi Erik,

On Wed, 16 Nov 2022 16:57:59 +0100
Erik Kaashoek via time-nuts <time-nuts at lists.febo.com> wrote:

> As often with your advice, I'm not smart enough to understand.
> The digital down mixing to zero Hz is done with I/Q mixers where sin/cos 
> of the internal LO is multiplied with the input signals and then average 
> over some samples to get I and Q of the signal vector as the output 
> frequency is zero Hz.

Exactly. Going to zero Hz means that the LO frequency is the same as the
RF frequency. Which means the (complex) output gives you a vector that points
into the direction of the phase difference between the RF and LO signal.

> I would expect I would need a separate set of I/Q mixers for the side 
> channel and by summing over many samples the noise would be reduced 
> sufficiently to get a relevant I and Q signal even if the side channel 
> has 40dB lower amplitude. 

Yes. You are looking for changes due to temperature fluctuation, which are slow.
A time constant in the  milli-second range is sufficient.

> I may have used the word FFT to describe the 
> operation of the I/Q mixers as computationally they look a lot like a 
> single bucket FFT

Yes, there are many ways how to implement an FFT in hardware. One of them
is using narrow band filters made out of (damped) oscillator structures.
And that is, in its working principle, quite close to what the down-mixing
approach does. 

On Wed, 16 Nov 2022 18:28:33 +0100
Erik Kaashoek via time-nuts <time-nuts at lists.febo.com> wrote:

> I went ahead and did a fairly simple implementation of the side channel. 
> Both channels show, apart from the noise, the same phase drift in the 
> order of some ps. 

So you got a result that is close to what we expected to see.

> This seems to confirm the drift originates in the mixers.

Be careful with this conclusion. The drift can originate anywhere
where the signals travel different paths. It could be equally well the
clock of your two ADCs that's the culprit, because they too take different
paths after the splitter. Figuring out which part is the dominant source
of delay takes a lot of care and experimental skill.


> Now I need a 3 channel DSS to test this. Maybe I can use the 
> 10MHz ref out as the 3rd channel. And I have to find a way to inject the 
> side channel without creating additional leakage between the two main 
> channels.

Be also careful with signals that are correlated to your clock or LO signals.
These can show higher or lower noise than the actually measured signals.

The injection needs to be done in a way that isolates the two paths. You can
either use some isolation amplifier that are closely matched, or start with
a strong signal and add some 30dB damping in the two paths after the splitter.

				Attila Kinali

-- 
In science if you know what you are doing you should not be doing it.
In engineering if you do not know what you are doing you should not be doing it.
        -- Richard W. Hamming, The Art of Doing Science and Engineering