[time-nuts] Re: pulling some crystals

[Jim Lux]

That’s true for a vanilla phase accumulator -> lookup -> DAC  flavor of DDS.  These days, in FPGA implementations register lengths aren’t so much a problem, there are clever sin/cos calculation/lookup schemes to make them fit, etc.

Once you’re through that, there’s a whole raft of clever techniques to reduce or move spurs around.  If you are lucky enough to have slowly varying frequency/phase commands, you can do quite a bit of computation and load quite a few registers when you do an update, so you can have things like variable length sin/cos tables, multiple NCOs, varying coefficients in error filters. 

I would think that for a disciplined oscillator application, where the update rate might be “seconds”, there’s a lot of potential schemes that might not be feasible if you were modulating FM with a 1 MHz signal, or doing fancy PSK/FSK multitones.  Fortunately, the latter probably doesn’t have “need no spurs within 1 kHz of carrier” kind of requirements.


On Sat, 16 Dec 2023 09:30:07 -0500, Bob kb8tq via time-nuts <time-nuts at lists.febo.com> wrote:

Hi

A DDS is typically limited by two things:

1) The “linear binary” to sine (or cosine) conversion process.

2) The accuracy (and bit depth) of the ADC you use.

This is on top of the more normal Nyquist stuff that you would expect of any digital gizmo. Tossing a square wave in on top of the Nyquist issues normally turns things into a major mess spur wise.

Bob



> On Dec 15, 2023, at 5:36 PM, Hal Murray via time-nuts  wrote:
>
>
>> the ultimate clock is used as a sample rate clock for ADC, DAC, FPGA . this
>> drives everything. I can tweak say frequency offset of the system channels
>> that I generate with internal FPGA DDS, but producing a Part PerBillion
>> accurate sample rate conversion running at 393 MHz sample rate would be a
>> whole world of pain,
>
> Running a fast DDS in a FPGA is pretty easy once you see it. "Carry save
> adder" is the buzzword.
>
> The problem is how to make a wide adder go fast. The trick for a DDS is that
> all you need is the carry out of the adder. So put FFs along in the carry
> chain as needed to meet timing. That will delay the carry out by a cycle per
> FF but that doesn't matter for a DDS.
>
> Consider a 16 bit adder with one FF half way along the carry chain. When that FF is a 1, the high bits in the adder and the carry out will be a cycle behind the low bits. The next cycle they catch up. The carry out, the DDS signal, has the same pattern. It's just shifted in time. If you fed it to a spectrum analyzer you couldn't tell the difference.
>
> A part per billion is only 30 bits.
>
>
> --
> These are my opinions. I hate spam.
>
>
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