[time-nuts] Re: pulling some crystals

[Jim Lux]

On fast counter/adder implementations.
40 years ago, when I had to fight off the dinosaurs around the PC we did our FPGA designs on, we would use various schemes based on Linear Feedback Shift Registers to do fast DDS/NCO/Arbitrary Waveform generators. While fast counters are tricky in an FPGA (or discrete logic)  because of the carry propagation issues.  It’s easy to make a LFSR clock at the basic flipflop rate (since you can use distributed feedback to the stages, rather than a big XOR tree). So you load your waveform memory at memory locations corresponding to successive states of the LFSR. 
Then, you can also use the shift/add property of LFSRs (two identical LFSRs with a difference in phase/state can be added, to create the same sequence, but shifted by a different amount in time) to quickly modulate the instantaneous phase of the waveform.  For instance, if you have a 20 bit LFSR, you can get any of 20 different phases with a 20:1 mux. If you have 2 20 bit LFSRs, you’ve got 400 different combinations of phases selectable in one clock.
 


On Fri, 15 Dec 2023 14:36:43 -0800, Hal Murray via time-nuts <time-nuts at lists.febo.com> wrote:

> the ultimate clock is used as a sample rate clock for ADC, DAC, FPGA . this
> drives everything.  I can tweak say frequency offset of the system channels
> that I generate with internal FPGA DDS, but producing a Part PerBillion
> accurate sample rate conversion running at 393 MHz sample rate would be a
> whole world of pain,

Running a fast DDS in a FPGA is pretty easy once you see it. "Carry save
adder" is the buzzword.

The problem is how to make a wide adder go fast. The trick for a DDS is that
all you need is the carry out of the adder. So put FFs along in the carry
chain as needed to meet timing. That will delay the carry out by a cycle per
FF but that doesn't matter for a DDS.

Consider a 16 bit adder with one FF half way along the carry chain. When that FF is a 1, the high bits in the adder and the carry out will be a cycle behind the low bits. The next cycle they catch up. The carry out, the DDS signal, has the same pattern. It's just shifted in time. If you fed it to a spectrum analyzer you couldn't tell the difference.

A part per billion is only 30 bits.


--
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