[time-nuts] Re: pulling some crystals

[Hal Murray]

glenlist at cortexrf.com.au said:
> But - one cannot use DDS generated clocks for high fidelity ADC/DAC from the
> FPGA outputs because the jitter on those generated clocks due to various
> internal processes is too high. Needs a crystal clock (which si how I do it)

If you have an FPGA, I assume you are doing some sort of DSP.  Can you tweak 
that software to compensate for the crystal frequency being a bit off?

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