[time-nuts] Re: pulling some crystals

[glen english LIST]

"

On 18/12/2023 2:54 pm, Hal Murray wrote:
> If you have an FPGA, I assume you are doing some sort of DSP.  Can you tweak
> that software to compensate for the crystal frequency being a bit off?
>
"

not without high logic cost (sample rate converter (SRC) with 120dB 
spurless performance over the whole 0 to fs spectrum.... running at 390 
MHz working over 15% of anywhere inside 0 to  Fs). and high power 
cost....heat.... .  that's non trivial !!!

it's easier having a good clock... Remember- this problem is currently 
SOLVED -Â  Currently I use a 24.576 off the shelf high quality TCXO for 
this job. I am merely bumping this up to 98.304 MHz to improve the phase 
noise of the synth driving the ADC and DAC.

 Â I can easily deal with sample rate (SR) errors down at say 40 Msps, 
but the SRC is complex because I need 0 to 0.45 Fs of workable 
performance, so that's a big long on the fly computed polyphase filter 
OH with LOTS of latency....  and down there, everything needs to run at 
powers of 2 clock speed, so I cannot just use my 10 MHz TCXO/GPSÂ  clock 
driving the FPGA ...Cant run the FPGA from the 10 MHz clock- need to use 
that for countre gating- I'd need to make 50 MHz from my 10 MHz  to feed 
the FPGA . One of those SiLabs clock chips could do that I guess for $5 
and 16 mm2...

anyway, I will let you guys know hopw I go once I am gone back to the 
oscillator.

thanks for all the input.

-glen