[time-nuts] Re: pulling some crystals

[Stewart Cobb]

Anyone considering DDS implementations in an FPGA should look at using the
CORDIC algorithm instead of sin/cos lookup tables. For short DAC output
words, a table is usually better and faster, but for long output words, the
table approach becomes unwieldy and the CORDIC starts to win.

If raw speed is the goal, is it's possible to build DDS counters and CORDIC
stages using serial arithmetic which will run at nearly the toggle speed of
the FPGA. Unfortunately, the number of CORDIC stages required by this trick
expands as roughly the square of the number of phase bits used from the
accumulator. Even though one CORDIC stage generally fits into one CLB, this
still becomes a lot of logic. And the control logic for all those serial
accumulators is tricky.

Just another tool for your toolbox.

Cheers!
--Stu