[time-nuts] Re: pulling some crystals

[Bob kb8tq]

Hi

One of the most basic issues is that a DDS chip is cheaper than an FPGA + DAC. Unless you already have a giant project in the FPGA that’s going to be an issue. If you do have a giant project in the FPGA, keeping the noise from that out of your DDS …. yikes !!!

Bob

> On Dec 18, 2023, at 8:20 AM, Stewart Cobb via time-nuts <time-nuts at lists.febo.com> wrote:
> 
> Anyone considering DDS implementations in an FPGA should look at using the
> CORDIC algorithm instead of sin/cos lookup tables. For short DAC output
> words, a table is usually better and faster, but for long output words, the
> table approach becomes unwieldy and the CORDIC starts to win.
> 
> If raw speed is the goal, is it's possible to build DDS counters and CORDIC
> stages using serial arithmetic which will run at nearly the toggle speed of
> the FPGA. Unfortunately, the number of CORDIC stages required by this trick
> expands as roughly the square of the number of phase bits used from the
> accumulator. Even though one CORDIC stage generally fits into one CLB, this
> still becomes a lot of logic. And the control logic for all those serial
> accumulators is tricky.
> 
> Just another tool for your toolbox.
> 
> Cheers!
> --Stu
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