[time-nuts] Re: pulling some crystals

[glen english LIST]

Interesting on the DRO. what is dirty is any clock or signal that comes 
out of an FPGA pin (it is subject to internal path jitter) . That's why 
we always retime the  data and frame clocks  into a DAC with a clean 
separate clock.

BTW I bought a PN2060 Rev 1.1 , it will arrive in another week. WHile I 
built myself a cross-correlative phase noise analyser using my junkbox, 
this product at USD650 inc shipping is just too easy...

On 18/12/2023 7:00 am, Jim Lux via time-nuts wrote:
>
> On Sat, 16 Dec 2023 10:19:47 +1100, glenlist via time-nuts<time-nuts at lists.febo.com>  wrote:
>
> frequency tweaks of generated signals is easy as you point out . (I have
> DDS carrier generators in the fabric for generating baseband signal
> sources )
>
> But - one cannot use DDS generated clocks for high fidelity ADC/DAC from
> the FPGA outputs because the jitter on those generated clocks due to
> various internal processes is too high. Needs a crystal clock (which si
> how I do it) .
>
> —-> Yes, the raw DDS output is pretty ratty - typically, you’d use that to lock a nice quiet crystal with good close in, but sufficient pull range (recognizing that this is sort of counter to each other - good close in implies high Q, pull range implies low Q).  We fought this for years at JPL with DROs trying to make something that would have 100 MHz (or even 50 MHz) tuning range at 7 and 8.4 GHz, and have good close in phase noise for good ranging performance.
>
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>
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