[time-nuts] Re: pulling some crystals

[Jim Lux]

 


On Sat, 16 Dec 2023 10:19:47 +1100, glenlist via time-nuts <time-nuts at lists.febo.com> wrote:

frequency tweaks of generated signals is easy as you point out . (I have
DDS carrier generators in the fabric for generating baseband signal
sources )

But - one cannot use DDS generated clocks for high fidelity ADC/DAC from
the FPGA outputs because the jitter on those generated clocks due to
various internal processes is too high. Needs a crystal clock (which si
how I do it) .

—-> Yes, the raw DDS output is pretty ratty - typically, you’d use that to lock a nice quiet crystal with good close in, but sufficient pull range (recognizing that this is sort of counter to each other - good close in implies high Q, pull range implies low Q).  We fought this for years at JPL with DROs trying to make something that would have 100 MHz (or even 50 MHz) tuning range at 7 and 8.4 GHz, and have good close in phase noise for good ranging performance.

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